Patents by Inventor Kun-Hsien Lee
Kun-Hsien Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190355849Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first gate structures, a plurality of second gate structures, a first strained region, and a second strained region. The substrate has a first region and a second region. The first gate structures are disposed in the first region on the substrate. The second gate structures are disposed in the second region on the substrate. The first strained region is formed in the substrate and has a first distance from an adjacent first gate structure. The second strained region is formed in the substrate and has a second distance from an adjacent second gate structure, wherein the second distance is greater than the first distance.Type: ApplicationFiled: August 1, 2019Publication date: November 21, 2019Applicant: United Microelectronics Corp.Inventors: LING-CHUN CHOU, Kun-Hsien Lee
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Patent number: 10439066Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first gate structures, a plurality of second gate structures, a first strained region, and a second strained region. The substrate has a first region and a second region. The first gate structures are disposed in the first region on the substrate. The second gate structures are disposed in the second region on the substrate. The first strained region is formed in the substrate and has a first distance from an adjacent first gate structure. The second strained region is formed in the substrate and has a second distance from an adjacent second gate structure, wherein the second distance is greater than the first distance.Type: GrantFiled: September 29, 2017Date of Patent: October 8, 2019Assignee: United Miccroelectronics Corp.Inventors: Ling-Chun Chou, Kun-Hsien Lee
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Publication number: 20190067480Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first gate structures, a plurality of second gate structures, a first strained region, and a second strained region. The substrate has a first region and a second region. The first gate structures are disposed in the first region on the substrate. The second gate structures are disposed in the second region on the substrate. The first strained region is formed in the substrate and has a first distance from an adjacent first gate structure. The second strained region is formed in the substrate and has a second distance from an adjacent second gate structure, wherein the second distance is greater than the first distance.Type: ApplicationFiled: September 29, 2017Publication date: February 28, 2019Applicant: United Microelectronics Corp.Inventors: Ling-Chun Chou, Kun-Hsien Lee
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Patent number: 9978745Abstract: A bipolar junction transistor (BJT) includes a semiconductor substrate and a first isolation structure. The semiconductor substrate includes a first fin structure disposed in an emitter region, a second fin structure disposed in a base region, and a third fin structure disposed in a collector region. The first, the second, and the third fin structures are elongated in a first direction respectively. The base region is adjacent to the emitter region, and the base region is located between the emitter region and the collector region. The first isolation structure is disposed between the first fin structure and the second fin structure, and a length of the first isolation structure in the first direction is shorter than or equal to 40 nanometers. An effective base width of the BJT may be reduced by the disposition of the first isolation structure, and a current gain of the BJT may be enhanced accordingly.Type: GrantFiled: October 11, 2016Date of Patent: May 22, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuan-Ti Wang, Ling-Chun Chou, Kun-Hsien Lee
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Publication number: 20180068998Abstract: A bipolar junction transistor (BJT) includes a semiconductor substrate and a first isolation structure. The semiconductor substrate includes a first fin structure disposed in an emitter region, a second fin structure disposed in a base region, and a third fin structure disposed in a collector region. The first, the second, and the third fin structures are elongated in a first direction respectively. The base region is adjacent to the emitter region, and the base region is located between the emitter region and the collector region. The first isolation structure is disposed between the first fin structure and the second fin structure, and a length of the first isolation structure in the first direction is shorter than or equal to 40 nanometers. An effective base width of the BJT may be reduced by the disposition of the first isolation structure, and a current gain of the BJT may be enhanced accordingly.Type: ApplicationFiled: October 11, 2016Publication date: March 8, 2018Inventors: Kuan-Ti Wang, Ling-Chun Chou, Kun-Hsien Lee
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Patent number: 9853021Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a shallow trench isolation (STI) adjacent to the first fin-shaped structure; and forming a gate structure on the first fin-shaped structure and the STI. Preferably, the gate structure comprises a left portion and the right portion and the work functions in the left portion and the right portion are different.Type: GrantFiled: June 6, 2017Date of Patent: December 26, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuan-Ti Wang, Ling-Chun Chou, Kun-Hsien Lee
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Patent number: 9799770Abstract: The present invention provides a FinFET device, including at least one fin structure, wherein the fin structure has a first-type well region, and a second-type well region adjacent to the first-type well region, a trench located in the fin structure and disposed between the first-type well region and the second-type well region, an insulating layer disposed in the trench, and a metal gate crossing over and disposed on the insulating layer.Type: GrantFiled: March 9, 2016Date of Patent: October 24, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ting-Yao Lin, Ling-Chun Chou, Kun-Hsien Lee
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Publication number: 20170243977Abstract: The present invention provides a FinFET device, including at least one fin structure, wherein the fin structure has a first-type well region, and a second-type well region adjacent to the first-type well region, a trench located in the fin structure and disposed between the first-type well region and the second-type well region, an insulating layer disposed in the trench, and a metal gate crossing over and disposed on the insulating layer.Type: ApplicationFiled: March 9, 2016Publication date: August 24, 2017Inventors: Ting-Yao Lin, Ling-Chun Chou, Kun-Hsien Lee
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Patent number: 9502260Abstract: The present invention provides a method for forming a semiconductor structure, including: firstly, providing a substrate, a fin structure being disposed on the substrate, a gate structure crossing over the fin structure, and a first hard mask being disposed on the top surface of the gate structure. Next, a dielectric layer is formed, covering the substrate, the fin structure and the gate structure. Afterwards, a second hard mask is formed on the top surface of the first hard mask, where the width of the second hard mask is larger than the width of the first hard mask, a bottom surface of the second hard mask and a top surface of the first hard mask are on the same level. An etching process is then performed to remove parts of the dielectric and parts of the fin structure.Type: GrantFiled: January 19, 2015Date of Patent: November 22, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-An Huang, Kun-Hsien Lee
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Publication number: 20160313493Abstract: The present disclosure relates to a light guide plate and a display apparatus having the same. The light guide plate includes a transparent light guide plate body and a plurality of microstructures. The transparent light guide plate body has a first surface and a second surface opposite to the first surface, wherein the first surface has a surface roughness of less than or equal to 100 nm. The microstructures are disposed on the first surface. A light beam from the transparent light guide plate body is reflected by the microstructures, and another light beam from the transparent light guide plate body passes through the first surface between the microstructures.Type: ApplicationFiled: April 27, 2015Publication date: October 27, 2016Inventors: KUN-HSIEN LEE, MING-HSIEN WU, YI-HSUAN TAI, CHIN-MING WANG, HUNG-WEN WANG, HUANG-CHIEH CHIU
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Publication number: 20160189970Abstract: The present invention provides a method for forming a semiconductor structure, including: firstly, providing a substrate, a fin structure being disposed on the substrate, a gate structure crossing over the fin structure, and a first hard mask being disposed on the top surface of the gate structure. Next, a dielectric layer is formed, covering the substrate, the fin structure and the gate structure. Afterwards, a second hard mask is formed on the top surface of the first hard mask, where the width of the second hard mask is larger than the width of the first hard mask, a bottom surface of the second hard mask and a top surface of the first hard mask are on the same level. An etching process is then performed to remove parts of the dielectric and parts of the fin structure.Type: ApplicationFiled: January 19, 2015Publication date: June 30, 2016Inventors: Shih-An Huang, Kun-Hsien Lee
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Publication number: 20140348416Abstract: A stereo image rectification apparatus includes: an input unit, for receiving a first image from a first camera and a second image from a second camera, wherein the first and the second camera are affine cameras; a feature point determination unit, for determining at least one first feature point on the first image and at least one second feature point on the second image, wherein both the first feature point on the first image and the second feature point on the second image correspond to the same imaginary object; and a warping matrix establishing unit, for establishing a warping matrix for mapping the first image to the second image by: calculating the elements of the warping matrix in regard to the mapping between the x- and y-coordinates of the first feature points and the y-coordinates of the second feature pointsType: ApplicationFiled: May 23, 2013Publication date: November 27, 2014Applicant: HIMAX MEDIA SOLUTIONS, INC.Inventor: Kun-Hsien Lee
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Publication number: 20140348428Abstract: A dynamic range-adjustment apparatus is provided. The apparatus includes: an input unit for receiving an original image; an histogram equalization unit, coupled to the input unit, for performing contrast enhancement on the original image to produce a contrast-enhanced image; a factor-determination unit, coupled to the input unit and the histogram equalization unit, for determining a first factor based on the gray level of a pixel of the original image and the tone of the corresponding pixel of the contrast-enhanced image; and an adjustment unit, coupled to the input unit, the histogram equalization unit and the factor-determination unit.Type: ApplicationFiled: May 24, 2013Publication date: November 27, 2014Applicant: HIMAX MEDIA SOLUTIONS, INC.Inventor: Kun-Hsien Lee
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Patent number: 8823109Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a N-type well, a gate disposed on the N-type well, a spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, a P-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the P-type source/drain region and the first lightly doped region and a silicide layer disposed on the silicon cap layer, and covering only a portion of the silicon cap layer.Type: GrantFiled: January 9, 2013Date of Patent: September 2, 2014Assignee: United Microelectronics Corp.Inventors: Wen-Han Hung, Tsai-Fu Chen, Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Ta-Kang Lo, Tzyy-Ming Cheng
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Patent number: 8711052Abstract: An antenna support device for supporting an antenna is disclosed. The antenna support device includes a support arm, a holder mounted on the support arm, a first connecting member rotatably connected to the holder around a first axis, a second connecting member rotatably connected to the first connecting member around a second axis, and an antenna bracket fixed on the second connecting member, wherein the antenna is fixed on the antenna bracket.Type: GrantFiled: June 2, 2011Date of Patent: April 29, 2014Assignee: Wistron NeWeb CorporationInventors: Yi-Chieh Lin, Kun-Hsien Lee, Hung-Yuan Lin, San-Yi Kuo
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Patent number: 8664073Abstract: A method for fabricating complimentary metal-oxide-semiconductor field-effect transistor is disclosed. The method includes the steps of: (A) forming a first gate structure and a second gate structure on a substrate; (B) performing a first co-implantation process to define a first type source/drain extension region depth profile in the substrate adjacent to two sides of the first gate structure; (C) forming a first source/drain extension region in the substrate adjacent to the first gate structure; (D) performing a second co-implantation process to define a first pocket region depth profile in the substrate adjacent to two sides of the second gate structure; (E) performing a first pocket implantation process to form a first pocket region adjacent to two sides of the second gate structure.Type: GrantFiled: January 4, 2011Date of Patent: March 4, 2014Assignee: United Microelectronics Corp.Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Meng-Yi Wu, Tzyy-Ming Cheng
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Patent number: 8486795Abstract: A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.Type: GrantFiled: April 12, 2012Date of Patent: July 16, 2013Assignee: United Microelectronics Corp.Inventors: Wen-Han Hung, Tsai-Fu Chen, Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Ta-Kang Lo, Tzyy-Ming Cheng
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Patent number: 8390073Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a P-type well, a gate disposed on the P-type well, a first spacer disposed on the gate, an N-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the N-type source/drain region, a second spacer around the first spacer and the second spacer directly on and covering a portion of the silicon cap layer and a silicide layer disposed on the silicon cap layer.Type: GrantFiled: April 18, 2012Date of Patent: March 5, 2013Assignee: United Microelectronics Corp.Inventors: Wen-Han Hung, Tsai-Fu Chen, Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Ta-Kang Lo, Tzyy-Ming Cheng
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Publication number: 20120212394Abstract: An antenna support device for supporting an antenna is disclosed. The antenna support device includes a support arm, a holder mounted on the support arm, a first connecting member rotatably connected to the holder around a first axis, a second connecting member rotatably connected to the first connecting member around a second axis, and an antenna bracket fixed on the second connecting member, wherein the antenna is fixed on the antenna bracket.Type: ApplicationFiled: June 2, 2011Publication date: August 23, 2012Inventors: Yi-Chieh Lin, Kun-Hsien Lee, Hung-Yuan Lin, San-Yi Kuo
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Publication number: 20120199890Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a P-type well, a gate disposed on the P-type well, a first spacer disposed on the gate, an N-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the N-type source/drain region, a second spacer around the first spacer and the second spacer directly on and covering a portion of the silicon cap layer and a silicide layer disposed on the silicon cap layer.Type: ApplicationFiled: April 18, 2012Publication date: August 9, 2012Inventors: Wen-Han Hung, Tsai-Fu Chen, Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Ta-Kang Lo, Tzyy-Ming Cheng