Patents by Inventor Kun-Hsu Shen
Kun-Hsu Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9195784Abstract: The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.Type: GrantFiled: April 1, 2011Date of Patent: November 24, 2015Assignee: Cadence Design Systems, Inc.Inventors: Ping-Sheng Tseng, Sharon Sheau-Pyng Lin, Quincy Kun-Hsu Shen, Mike Mon Yen Tsai, Steven Wang
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Patent number: 8244512Abstract: The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.Type: GrantFiled: September 12, 2001Date of Patent: August 14, 2012Assignee: Cadence Design Systems, Inc.Inventors: Ping-Sheng Tseng, Sharon Sheau-Pyng Lin, Quincy Kun-Hsu Shen, Mike Mon Yen Tsai, Steven Wang
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Publication number: 20110307233Abstract: The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.Type: ApplicationFiled: April 1, 2011Publication date: December 15, 2011Inventors: Ping-Sheng Tseng, Sharon Sheau-Pyng Lin, Quincy Kun-Hsu Shen, Mike Mon Yen Tsai, Steven Wang
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Patent number: 7480606Abstract: In the VCD-On-Demand system, the EDA tool has the following attributes: (1) RCC-based parallel simulation history compression and recording, (2) RCC-based parallel simulation history decompression and VCD file generation, and (3) On-demand software regeneration for a selected simulation target range without simulation rerun. When the user selects a simulation session range, the RCC System records a highly compressed version of the primary inputs from the test bench process. The user then selects a narrower region, the simulation target range, within the simulation session range for a more focused analysis. The RCC System dumps the hardware state information of the hardware model into a VCD file. The RCC System then allows the user to proceed directly to view the VCD file from the beginning of the simulation target range without having to rerun the entire simulation from the beginning of the simulation session range.Type: GrantFiled: May 20, 2005Date of Patent: January 20, 2009Assignee: Versity Design, Inc.Inventors: Ping-Sheng Tseng, Yogesh Kumar Goel, Kun-Hsu Shen
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Publication number: 20060117274Abstract: The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.Type: ApplicationFiled: July 30, 2001Publication date: June 1, 2006Inventors: Ping-Sheng Tseng, Yogesh Goel, Su-Jen Hwang, James Lee, Kun-Hsu Shen
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Publication number: 20050228630Abstract: The disclosed technology is called VCD on demand. In a typical system, the EDA tool incorporating the VCD on-demand technology has the following high level attributes: (1) RCC-based parallel simulation history compression and recording, (2) RCC-based parallel simulation history decompression and VCD file generation, and (3) On-demand software regeneration for a selected simulation target range and design review without simulation rerun. Each of these attributes will be discussed in greater detail below. When the user selects a simulation session range, the RCC System records a highly compressed version of the primary inputs from the test bench process. The user then selects a narrower region, called the simulation target range, within the simulation session range for a more focused analysis. The RCC System dumps the hardware state information (i.e., primary outputs) of the hardware model into a VCD file.Type: ApplicationFiled: May 20, 2005Publication date: October 13, 2005Inventors: Ping-Sheng Tseng, Yogesh Goel, Kun-Hsu Shen
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Patent number: 6321366Abstract: The disclosed devices are several forms of a timing insensitive glitch-free (TIGF) logic device. The TIGF logic device can take the form of any latch or edge-triggered flip-flop. In one embodiment, a trigger signal is provided to update the TIGF logic device. The trigger signal is provided during a short trigger period that occurs at adjacent times from the evaluation period. In latch form, the TIGF latch includes a flip-flop that holds the current state of the TIGF latch until a trigger signal is received. A multiplexer is also provided to receive the new input value and the old stored value. The enable signal functions as the selector signal for the multiplexer. Because the trigger signal controls the updating of the TIGF latch, the data at D input to the TIGF latch and the control data at the enable input can arrive in any order without suffering from hold time violations.Type: GrantFiled: August 31, 1998Date of Patent: November 20, 2001Assignee: Axis Systems, Inc.Inventors: Ping-Sheng Tseng, Sharon Sheau-Ping Lin, Quincy Kun-Hsu Shen
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Patent number: 6134516Abstract: The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present.Type: GrantFiled: February 5, 1998Date of Patent: October 17, 2000Assignee: Axis Systems, Inc.Inventors: Steven Wang, Ping-Sheng Tseng, Sharon Sheau-Pyng Lin, Ren-Song Tsay, Richard Yachyang Sun, Quincy Kun-Hsu Shen, Mike Mon Yen Tsai
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Patent number: 6009256Abstract: The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present.Type: GrantFiled: May 2, 1997Date of Patent: December 28, 1999Assignee: Axis Systems, Inc.Inventors: Ping-Sheng Tseng, Sharon Sheau-Pyng Lin, Quincy Kun-Hsu Shen, Richard Yachyang Sun, Mike Mon Yen Tsai, Ren-Song Tsay, Steven Wang