Patents by Inventor Kun-Huang Yu
Kun-Huang Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9236471Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation. The bottom surface of the second portion of the conductive plug is covered by the isolation.Type: GrantFiled: April 15, 2014Date of Patent: January 12, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chiu-Te Lee, Ke-Feng Lin, Shu-Wen Lin, Kun-Huang Yu, Chih-Chung Wang, Te-Yuan Wu
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Patent number: 9196695Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.Type: GrantFiled: May 8, 2014Date of Patent: November 24, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kun-Huang Yu, Shih-Yin Hsiao, Wen-Fang Lee, Shu-Wen Lin, Kuan-Chuan Chen
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Publication number: 20150287797Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.Type: ApplicationFiled: May 8, 2014Publication date: October 8, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kun-Huang Yu, Shih-Yin Hsiao, Wen-Fang Lee, Shu-Wen Lin, Kuan-Chuan Chen
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Publication number: 20150145034Abstract: A LDMOS structure including a semiconductor substrate, a drain region, a lightly doped drain (LDD) region, a source region and a gate structure is provided. The substrate has a trench. The drain region is formed in the semiconductor substrate under the trench. A LDD region is formed in the semiconductor substrate at a sidewall of the trench. The source region is formed in the semiconductor substrate. The gate structure is formed on a surface of the semiconductor substrate above the LDD region between the drain region and the source region. A method for manufacturing the LDMOS structure is also provided.Type: ApplicationFiled: November 24, 2013Publication date: May 28, 2015Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Chiu-Te Lee, Kuan-Yu Chen, Ming-Shun Hsu, Chih-Chung Wang, Ke-Feng Lin, Shu-Wen Lin, Shih-Teng Huang, Kun-Huang Yu
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Patent number: 8896057Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well and a second well respectively having the first and second conductive types formed in the deep well, and extending down from the surface of the substrate; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion comprising at least two fingers penetrating into the isolation, and the fingers spaced apart and electrically connected to each other.Type: GrantFiled: May 14, 2013Date of Patent: November 25, 2014Assignee: United Microelectronics Corp.Inventor: Kun-Huang Yu
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Publication number: 20140339632Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well and a second well respectively having the first and second conductive types formed in the deep well, and extending down from the surface of the substrate; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion comprising at least two fingers penetrating into the isolation, and the fingers spaced apart and electrically connected to each other.Type: ApplicationFiled: May 14, 2013Publication date: November 20, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventor: Kun-Huang Yu
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Publication number: 20140225192Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation. The bottom surface of the second portion of the conductive plug is covered by the isolation.Type: ApplicationFiled: April 15, 2014Publication date: August 14, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chiu-Te Lee, Ke-Feng Lin, Shu-Wen Lin, Kun-Huang Yu, Chih-Chung Wang, Te-Yuan Wu
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Patent number: 8766358Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation.Type: GrantFiled: April 24, 2012Date of Patent: July 1, 2014Assignee: United Microelectronics Corp.Inventors: Chiu-Te Lee, Ke-Feng Lin, Shu-Wen Lin, Kun-Huang Yu, Chih-Chung Wang, Te-Yuan Wu
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Patent number: 8729631Abstract: A MOS transistor is described, including: a source region and a drain region in a semiconductor substrate, an isolation between the source region and the drain region, a first gate conductor between the source region and the isolation, at least one conductive plug electrically connected to the first gate conductor and penetrating into the isolation, and at least one second gate conductor on the isolation, which is electrically connected to the first gate conductor and the at least one conductive plug. One of the at least one conductive plug is between the first gate conductor and the at least one second gate conductor.Type: GrantFiled: August 28, 2012Date of Patent: May 20, 2014Assignee: United Microelectronics Corp.Inventors: Kun-Huang Yu, Chin-Fu Chen
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Patent number: 8704304Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a dielectric layer, a dielectric structure and an electrode structure. The dielectric layer is on an upper substrate surface of the semiconductor substrate. The dielectric structure and the semiconductor substrate have opposing first and second interfaces therebetween. The electrode structure comprises an electrode truck portion and at least one electrode branch portion. The at least one electrode branch portion is extended from the electrode truck portion down into the dielectric structure. The at least one electrode branch portion and the first interface have the smallest gap distance substantially bigger than 300 ? therebetween.Type: GrantFiled: October 5, 2012Date of Patent: April 22, 2014Assignee: United Microelectronics Corp.Inventor: Kun-Huang Yu
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Publication number: 20140097492Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a dielectric layer, a dielectric structure and an electrode structure. The dielectric layer is on an upper substrate surface of the semiconductor substrate. The dielectric structure and the semiconductor substrate have opposing first and second interfaces therebetween. The electrode structure comprises an electrode truck portion and at least one electrode branch portion. The at least one electrode branch portion is extended from the electrode truck portion down into the dielectric structure. The at least one electrode branch portion and the first interface have the smallest gap distance substantially bigger than 300 ? therebetween.Type: ApplicationFiled: October 5, 2012Publication date: April 10, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventor: Kun-Huang Yu
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Publication number: 20140061791Abstract: A MOS transistor is described, including: a source region and a drain region in a semiconductor substrate, an isolation between the source region and the drain region, a first gate conductor between the source region and the isolation, at least one conductive plug electrically connected to the first gate conductor and penetrating into the isolation, and at least one second gate conductor on the isolation, which is electrically connected to the first gate conductor and the at least one conductive plug. One of the at least one conductive plug is between the first gate conductor and the at least one second gate conductor.Type: ApplicationFiled: August 28, 2012Publication date: March 6, 2014Applicant: United Microelectronics Corp.Inventors: KUN-HUANG YU, Chin-Fu Chen
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Publication number: 20130277742Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation.Type: ApplicationFiled: April 24, 2012Publication date: October 24, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chiu-Te Lee, Ke-Feng Lin, Shu-Wen Lin, Kun-Huang Yu, Chih-Chung Wang, Te-Yuan Wu