Patents by Inventor Kun Sik Park

Kun Sik Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220020671
    Abstract: The present invention minimizes parasitic inductance at the time of packaging a semiconductor that requires high efficiency and high-speed switching driving. In implementing a semiconductor package composed of one or more switching devices and one or more diode devices, the present invention provides a flip-stack structure in which a switching device is mounted on an insulating substrate or a metal frame, a flat metal is bonded onto the switching device, and a diode device is flipped and stacked on the flat metal, and accordingly, the flat metal with a large area is used for connection between the devices and between the devices and the insulating substrate, thereby minimizing parasitic inductance generated at a time of semiconductor packaging and automating the entire process of the semiconductor packaging.
    Type: Application
    Filed: July 20, 2021
    Publication date: January 20, 2022
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Dong Yun JUNG, Hyun Gyu JANG, Sung Kyu KWON, Kun Sik PARK, Jong Il WON, Seong Hyun LEE, Jong Won LIM, Doo Hyung CHO
  • Publication number: 20210408265
    Abstract: The present invention forms an off-FET channel having a uniform and short length by using a self-align process of a method of forming and recessing a spacer, thereby enhancing the current driving capability of an off-FET and the uniformity of a device operation.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 30, 2021
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Kun Sik PARK, Jong Il WON, Doo Hyung CHO, Hyun Gyu JANG, Dong Yun JUNG
  • Publication number: 20210335681
    Abstract: A ceramic stacked semiconductor package and a method of packaging a ceramic stacked semiconductor is disclosed. Inner walls of junctions are formed between ceramic layers and a molding resin to have a non-uniform boundary shape (e.g., Z shape, an uneven shape, a zigzag shape, etc.) so that bonding areas and lengths of the molding resin and the ceramic layers are increased, and thus adhesion is improved and movement paths of moisture are increased, thereby improving anti-humidity property and reliability of the semiconductor package. Further, by arranging via-holes at different positions for each layer so as not to overlap each other between the layers, movement paths of moisture passing through the via-holes are increased, and thus the anti-humidity property and reliability of the stacked package are additionally improved.
    Type: Application
    Filed: March 30, 2021
    Publication date: October 28, 2021
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Hyun Gyu JANG, Dong Yun JUNG, Doo Hyung CHO, Kun Sik PARK, Jong Won LIM
  • Publication number: 20160284872
    Abstract: Provided is a Schottky diode including a substrate, a drift layer on the substrate, the drift layer comprising an active region and a periphery positioned at an edge of the active region, a junction termination layer on a boundary between the active region and the periphery, a first metal layer configured to cover a part of the active region and a part of the junction termination layer, and a second metal layer configured to cover the first metal layer and the active region, wherein the first metal layer and the second metal layer contact the drift layer to provide a Schottky junction, and the first metal layer has a higher Schottky barrier height than the second metal layer.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 29, 2016
    Inventors: Kun Sik PARK, Jong II WON, Doo Hyung CHO
  • Patent number: 9171621
    Abstract: A nonvolatile memory and a method of manufacturing a nonvolatile memory are disclosed. A nonvolatile memory according to an exemplary embodiment may include a deep well formed on a substrate, a first well formed within the deep well, a second well formed separately from the first well within the deep well, a first metal-oxide-semiconductor field-effect transistor (MOSFET) formed on the first well, and a second MOSFET formed on the second well. According to a method of manufacturing a nonvolatile memory according to an exemplary embodiment, a well region of a control MOSFET of a memory cell may be shared with a control MOSFET of an adjacent memory cell, or a well region of a tunneling MOSFET of a memory cell may be shared with a tunneling MOSFET of an adjacent memory cell, thereby reducing an area of the memory cells.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: October 27, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Kun Sik Park, Kyu Ha Baek
  • Patent number: 8981937
    Abstract: An RFID tag includes: an antenna receiving an RF signal from a reader; an AFE (analog front end) generating voltage using the RF signal; and one or more switches interposed between the antenna and the AFE and controlling the connection between the antenna and the AFE through the switch operation.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: March 17, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Ji Man Park, Lee Mi Do, Kyu Ha Baek, Kun Sik Park, Dong Pyo Kim, Jong Chang Woo, Zin Sig Kim, Joo Yeon Kim, Ye Sul Jeong, Yong Hyun Ham
  • Publication number: 20130294172
    Abstract: A nonvolatile memory and a method of manufacturing a nonvolatile memory are disclosed. A nonvolatile memory according to an exemplary embodiment may include a deep well formed on a substrate, a first well formed within the deep well, a second well formed separately from the first well within the deep well, a first metal-oxide-semiconductor field-effect transistor (MOSFET) formed on the first well, and a second MOSFET formed on the second well. According to a method of manufacturing a nonvolatile memory according to an exemplary embodiment, a well region of a control MOSFET of a memory cell may be shared with a control MOSFET of an adjacent memory cell, or a well region of a tunneling MOSFET of a memory cell may be shared with a tunneling MOSFET of an adjacent memory cell, thereby reducing an area of the memory cells.
    Type: Application
    Filed: April 26, 2013
    Publication date: November 7, 2013
    Inventors: Kun Sik PARK, Kyu Ha BAEK
  • Patent number: 8513655
    Abstract: An organic light emitting diode (OLED) and a method for manufacturing the same are provided. In the OLED, patterned metal electrodes are positioned on one or more of upper and lower portions of a light emission layer to allow light generated from the light emission layer to emit to an area between the patterned metal electrodes.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: August 20, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Lee Mi Do, Kun Sik Park, Ji Man Park, Dong Pyo Kim, Jin-Yeong Kang, Kyu Ha Baek
  • Patent number: 8486830
    Abstract: A via forming method that includes forming via-holes in a substrate is provided. The method includes putting the substrate, having the via-holes, in a first solution to fill the via-holes with the first solution. Metal particles are sunk into the via-holes by supplying a second solution containing the metal particles to the first solution. A first curing process of heat-treating the substrate is performed so as to form vias in the via-holes. A multi-chip package that includes the substrate having the vias is also provided.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: July 16, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Dong Pyo Kim, Kyu Ha Baek, Kun Sik Park, Lee Mi Do
  • Publication number: 20120161941
    Abstract: An RFID tag includes: an antenna receiving an RF signal from a reader; an AFE (analog front end) generating voltage using the RF signal; and one or more switches interposed between the antenna and the AFE and controlling the connection between the antenna and the AFE through the switch operation.
    Type: Application
    Filed: November 11, 2011
    Publication date: June 28, 2012
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Ji Man PARK, Lee Mi DO, Kyu Ha BAEK, Kun Sik PARK, Dong Pyo KIM, Jong Chang WOO, Zin Sig KIM, Joo Yeon KIM, Ye Sul JEONG, Yong Hyun HAM
  • Publication number: 20120057106
    Abstract: Provided are a polarizer and a liquid crystal display (LCD) in which wire grid polarizers are formed on a thin film transistor substrate and a color filter substrate, respectively, so that it is possible to reduce fabrication cost and the number of processes and decrease the thickness of the LCD. An LCD includes a thin film transistor substrate, a color filter substrate opposite to the thin film transistor substrate, and a liquid crystal layer positioned between the thin film transistor substrate and the color filter substrate. In the LCD, wire grid polarizing patterns are formed on the thin film transistor substrate and the color filter substrate, respectively.
    Type: Application
    Filed: September 7, 2011
    Publication date: March 8, 2012
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Kun Sik PARK, Kyu Ha Baek, Lee Mi Do
  • Patent number: 7994553
    Abstract: A complementary metal-oxide semiconductor (CMOS)-based planar type avalanche photo diode (APD) using a silicon epitaxial layer and a method of manufacturing the APD, the photo diode including: a substrate; a well layer of a first conductivity type formed in the substrate; an avalanche embedded junction formed in the well layer of the first conductivity type by low energy ion implantation; the silicon epitaxial layer formed in the avalanche embedded junction; a doping area of a second conductivity type opposite to the first conductive type, formed from a portion of a surface of the well layer of the first conductivity type in the avalanche embedded junction and forming a p-n junction; positive and negative electrodes formed on the doping area of the second conductivity type and the well layer of the first conductivity type separated from the doping area of the second conductivity type, respectively; and an oxide layer formed on an overall surface excluding a window where the positive and negative electrodes ar
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: August 9, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yong Sun Yoon, Kun Sik Park, Jong Moon Park, Bo Woo Kim, Jin Yeong Kang
  • Publication number: 20110147787
    Abstract: An organic light emitting diode (OLED) and a method for manufacturing the same are provided. In the OLED, patterned metal electrodes are positioned on one or more of upper and lower portions of a light emission layer to allow light generated from the light emission layer to emit to an area between the patterned metal electrodes.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 23, 2011
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Lee Mi DO, Kun Sik Park, Ji Man Park, Dong Pyo Kim, Jin Yeong Kang, Kyu Ha Baek
  • Publication number: 20110147468
    Abstract: Provided is a radio frequency identification (RFID) tag whose data can be stably read at a long distance on the basis of a passive RFID tag. The RFID tag includes a rechargeable unit charged to a predetermined voltage, and a power source including a direct current (DC) power source including a rectifier for converting an RF signal into DC power and a regulator for supplying a predetermined DC voltage, an interceptor disposed between the rechargeable unit and the DC power source to connecting or disconnecting the power to the rechargeable unit, and an overvoltage preventor connected to an output terminal of the DC power source in parallel.
    Type: Application
    Filed: December 16, 2010
    Publication date: June 23, 2011
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Ji Man PARK, Lee Mi Do, Kyu Ha Baek, Kun Sik Park, Dong Pyo Kim
  • Publication number: 20110097853
    Abstract: A via forming method is provided. The via forming method includes: forming via-holes in a substrate; putting the substrate having the via-holes in a first solution to fill the via-holes with the first solution; sinking the metal particles into the via-holes by supplying a second solution containing metal particles to the first solution, in which there is the substrate; and performing a first curing process of heat-treating the substrate having the via-holes filled with the metal particles so as to form vias in the via-holes. Further, a method of manufacturing a multi-chip package using the via forming method is provided.
    Type: Application
    Filed: July 13, 2010
    Publication date: April 28, 2011
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Dong Pyo KIM, Kyu Ha Baek, Kun Sik Park, Lee Mi Do
  • Patent number: 7855366
    Abstract: A BJT (bipolar junction transistor)-based uncooled IR sensor and a manufacturing method thereof are provided. The BJT-based uncooled IR sensor includes: a substrate; at least one BJT which is formed to be floated apart from the substrate; and a heat absorption layer which is formed on an upper surface of the at least one BJT, wherein the BJT changes an output value according heat absorbed through the heat absorption layer. Accordingly, it is possible to provide a BJT-based uncooled IR sensor capable of being implemented through a CMOS compatible process and obtaining more excellent temperature change detection characteristics.
    Type: Grant
    Filed: April 29, 2008
    Date of Patent: December 21, 2010
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Kun Sik Park, Yong Sun Yoon, Bo Woo Kim, Jin Yeong Kang, Jong Moon Park, Seong Wook Yoo
  • Publication number: 20090321641
    Abstract: A BJT (bipolar junction transistor)-based uncooled IR sensor and a manufacturing method thereof are provided. The BJT-based uncooled IR sensor includes: a substrate; at least one BJT which is formed to be floated apart from the substrate; and a heat absorption layer which is formed on an upper surface of the at least one BJT, wherein the BJT changes an output value according heat absorbed through the heat absorption layer. Accordingly, it is possible to provide a BJT-based uncooled IR sensor capable of being implemented through a CMOS compatible process and obtaining more excellent temperature change detection characteristics.
    Type: Application
    Filed: April 29, 2008
    Publication date: December 31, 2009
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Kun Sik PARK, Yong Sun YOON, Bo Woo KIM, Jin Yeong KANG, Jong Moon PARK, Seong Wook YOO
  • Publication number: 20090146238
    Abstract: A complementary metal-oxide semiconductor (CMOS)-based planar type avalanche photo diode (APD) using a silicon epitaxial layer and a method of manufacturing the APD, the photo diode including: a substrate; a well layer of a first conductivity type formed in the substrate; an avalanche embedded junction formed in the well layer of the first conductivity type by low energy ion implantation; the silicon epitaxial layer formed in the avalanche embedded junction; a doping area of a second conductivity type opposite to the first conductive type, formed from a portion of a surface of the well layer of the first conductivity type in the avalanche embedded junction and forming a p-n junction; positive and negative electrodes formed on the doping area of the second conductivity type and the well layer of the first conductivity type separated from the doping area of the second conductivity type, respectively; and an oxide layer formed on an overall surface excluding a window where the positive and negative electrodes ar
    Type: Application
    Filed: August 20, 2008
    Publication date: June 11, 2009
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Yong Sun Yoon, Kun Sik Park, Jong Moon Park, Bo Woo Kim, Jin Yeong Kang
  • Patent number: 7190432
    Abstract: Provided is a wafer exposure apparatus used in a semiconductor device manufacturing process, the exposure apparatus including: a reflective mirror for reflecting light provided from a light source; an optical path changer for changing a path of the light provided from the reflective mirror; first mirrors installed at both sides of the optical path changer to change the path of the light; second mirrors installed at both sides of a material to change the path of the light; and third mirrors installed at both sides of a mask to enter the light reflected by the first mirrors to the mask and to enter the light passed through the mask into the second mirrors, whereby it is possible to continuously expose one surface, both surfaces or a specific surface of a wafer in a state that the wafer is once aligned.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: March 13, 2007
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sang Gi Kim, Ju Wook Lee, Jong Moon Park, Seong Wook Yoo, Kun Sik Park, Yong Sun Yoon, Yoon Kyu Bae, Byung Won Lim, Jin Gun Koo, Boo Woo Kim
  • Patent number: 7141464
    Abstract: Provided is a method of fabricating a T-type gate including the steps of: forming a first photoresist layer, a blocking layer and a second photoresist layer to a predetermined thickness on a substrate, respectively; forming a body pattern of a T-type gate on the second photoresist layer and the blocking layer; exposing a predetermined portion of the second photoresist layer to form a head pattern of the T-type gate, and performing a heat treatment process to generate cross linking at a predetermined region of the second photoresist layer except for the head pattern of the T-type gate; performing an exposure process on an entire surface of the resultant structure, and then removing the exposed portion; and forming a metal layer of a predetermined thickness on an entire surface of the resultant structure, and then removing the first photoresist layer, the blocking layer, the predetermined region of the second photoresist layer in which the cross linking are generated, and the metal layer, whereby it is possible
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: November 28, 2006
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jong Moon Park, Kun Sik Park, Seong Wook Yoo, Yong Sun Yoon, Sang Gi Kim, Yoon Kyu Bae, Byung Won Lim, Jin Gun Koo, Bo Woo Kim