Patents by Inventor Kun Sik Park
Kun Sik Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11957046Abstract: An electroluminescent device includes a first electrode and a second electrode facing each other; an emission layer disposed between the first electrode and the second electrode and including a plurality of quantum dots and a first hole transporting material having a substituted or unsubstituted C4 to C20 alkyl group attached to a backbone structure; a hole transport layer disposed between the emission layer and the first electrode and including a second hole transporting material; and an electron transport layer disposed between the emission layer and the second electrode.Type: GrantFiled: September 6, 2019Date of Patent: April 9, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Moon Gyu Han, Dae Young Chung, Kwanghee Kim, Eun Joo Jang, Chan Su Kim, Kun Su Park, Won Sik Yoon
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Patent number: 11925043Abstract: A quantum dot light-emitting device including first electrode and a second electrode, a quantum dot layer between the first electrode and the second electrode, a first electron transport layer and a second electron layer disposed between the quantum dot layer and the second electrode. The second electron transport layer is disposed between the quantum dot layer and the first electron transport layer, wherein each of the first electron transport layer and the second electron transport layer includes an inorganic material. A lowest unoccupied molecular orbital energy level of the second electron transport layer is shallower than a lowest unoccupied molecular orbital energy level of the first electron transport layer, and a lowest unoccupied molecular orbital energy level of the quantum dot layer is shallower than a lowest unoccupied molecular orbital energy level of the second electron transport layer. An electronic device including the quantum dot light-emitting device.Type: GrantFiled: October 16, 2020Date of Patent: March 5, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Moon Gyu Han, Heejae Lee, Eun Joo Jang, Tae Ho Kim, Kun Su Park, Won Sik Yoon, Hyo Sook Jang
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Patent number: 11784247Abstract: A MOS controlled thyristor device according to the concept of the present invention includes a substrate comprising a first surface and a second surface, which face each other, gate patterns disposed on the first surface, a cathode electrode configured to cover the gate patterns, and an anode electrode disposed on the second surface, The substrate includes a lower emitter layer having a first conductive type, a lower base layer having a second conductive type on the lower emitter layer, an upper base region provided in an upper portion of the lower emitter layer and having a first conductive type, wherein the upper base region is configured to expose a portion of a top surface of the lower base layer, an upper emitter region having a second conductive type and provided in an upper portion of the upper base region, a first doped region having a first conductive type and a second doped region surrounded by the first doped region and having a second conductive type, wherein the first and second doped regions areType: GrantFiled: June 10, 2021Date of Patent: October 10, 2023Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Kun Sik Park, Jong Il Won, Doo Hyung Cho, Dong Yun Jung, Hyun Gyu Jang
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Publication number: 20230231404Abstract: There is provided a battery system including: a controller; a main switch controlled by the controller to supply or cut off a voltage of a battery to a load; and a semiconductor pre-charger module including a semiconductor switch connected in parallel with the main switch and configured to supply or cut off the voltage of the battery to the load according to a control signal output from the controller, and a semiconductor switch driver configured to receive the control signal from the controller and output a single pulse signal for driving the semiconductor switch to turn on and off the semiconductor switch. Here, the semiconductor switch driver of the semiconductor pre-charger module includes an isolation element configured to electrically isolate the controller and the battery voltage, and the semiconductor switch of the semiconductor pre-charger module is a MOS-controlled thyristor (MCT).Type: ApplicationFiled: January 11, 2023Publication date: July 20, 2023Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Dong Yun JUNG, Kun Sik PARK, JONG IL WON, Hyun-Gyu JANG, Doohyung CHO, Jong-Won LIM
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Patent number: 11637192Abstract: The present invention forms an off-FET channel having a uniform and short length by using a self-align process of a method of forming and recessing a spacer, thereby enhancing the current driving capability of an off-FET and the uniformity of a device operation.Type: GrantFiled: June 23, 2021Date of Patent: April 25, 2023Assignee: Electronics and Telecommunications Research InstituteInventors: Kun Sik Park, Jong Il Won, Doo Hyung Cho, Hyun Gyu Jang, Dong Yun Jung
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Publication number: 20230087416Abstract: A MOS controlled thyristor device according to the concept of the present invention includes a substrate comprising a first surface and a second surface, which face each other, gate patterns disposed on the first surface, a cathode electrode configured to cover the gate patterns, and an anode electrode disposed on the second surface, The substrate includes a lower emitter layer having a first conductive type, a lower base layer having a second conductive type on the lower emitter layer, an upper base region provided in an upper portion of the lower emitter layer and having a first conductive type, wherein the upper base region is configured to expose a portion of a top surface of the lower base layer, an upper emitter region having a second conductive type and provided in an upper portion of the upper base region, a first doped region having a first conductive type and a second doped region surrounded by the first doped region and having a second conductive type, wherein the first and second doped regions areType: ApplicationFiled: June 10, 2021Publication date: March 23, 2023Inventors: Kun Sik PARK, Jong II WON, Doo Hyung CHO, Dong Yun JUNG, Hyun GYu Jang
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Publication number: 20220299554Abstract: The apparatus for ESD test includes a micro-controller unit client, a low voltage supply configured to output a low voltage on the basis of control by the micro-controller unit, a high voltage supply configured to output a high voltage on the basis of control by the micro-controller unit, and an ESD generator configured to generate an ESD voltage for an ESD test of a device under test (DUT) by using the low voltage and the high voltage, on the basis of control by the micro-controller unit. The ESD generator is a semiconductor integrated circuit module where a charging semiconductor switch, a discharging semiconductor switch, a switch driving block controlling a switching operation of each of the charging semiconductor switch and the discharging semiconductor switch, and a plurality of passive elements connected to the charging semiconductor switch and the discharging semiconductor switch are implemented as package, for generating the ESD voltage.Type: ApplicationFiled: October 26, 2021Publication date: September 22, 2022Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Dong Yun JUNG, Hyun Gyu JANG, Kun Sik PARK, JONG IL WON, Sung Kyu KWON, Jong Won LIM, Doo Hyung CHO
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Publication number: 20220020671Abstract: The present invention minimizes parasitic inductance at the time of packaging a semiconductor that requires high efficiency and high-speed switching driving. In implementing a semiconductor package composed of one or more switching devices and one or more diode devices, the present invention provides a flip-stack structure in which a switching device is mounted on an insulating substrate or a metal frame, a flat metal is bonded onto the switching device, and a diode device is flipped and stacked on the flat metal, and accordingly, the flat metal with a large area is used for connection between the devices and between the devices and the insulating substrate, thereby minimizing parasitic inductance generated at a time of semiconductor packaging and automating the entire process of the semiconductor packaging.Type: ApplicationFiled: July 20, 2021Publication date: January 20, 2022Applicant: Electronics and Telecommunications Research InstituteInventors: Dong Yun JUNG, Hyun Gyu JANG, Sung Kyu KWON, Kun Sik PARK, Jong Il WON, Seong Hyun LEE, Jong Won LIM, Doo Hyung CHO
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Publication number: 20210408265Abstract: The present invention forms an off-FET channel having a uniform and short length by using a self-align process of a method of forming and recessing a spacer, thereby enhancing the current driving capability of an off-FET and the uniformity of a device operation.Type: ApplicationFiled: June 23, 2021Publication date: December 30, 2021Applicant: Electronics and Telecommunications Research InstituteInventors: Kun Sik PARK, Jong Il WON, Doo Hyung CHO, Hyun Gyu JANG, Dong Yun JUNG
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Publication number: 20210335681Abstract: A ceramic stacked semiconductor package and a method of packaging a ceramic stacked semiconductor is disclosed. Inner walls of junctions are formed between ceramic layers and a molding resin to have a non-uniform boundary shape (e.g., Z shape, an uneven shape, a zigzag shape, etc.) so that bonding areas and lengths of the molding resin and the ceramic layers are increased, and thus adhesion is improved and movement paths of moisture are increased, thereby improving anti-humidity property and reliability of the semiconductor package. Further, by arranging via-holes at different positions for each layer so as not to overlap each other between the layers, movement paths of moisture passing through the via-holes are increased, and thus the anti-humidity property and reliability of the stacked package are additionally improved.Type: ApplicationFiled: March 30, 2021Publication date: October 28, 2021Applicant: Electronics and Telecommunications Research InstituteInventors: Hyun Gyu JANG, Dong Yun JUNG, Doo Hyung CHO, Kun Sik PARK, Jong Won LIM
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Publication number: 20160284872Abstract: Provided is a Schottky diode including a substrate, a drift layer on the substrate, the drift layer comprising an active region and a periphery positioned at an edge of the active region, a junction termination layer on a boundary between the active region and the periphery, a first metal layer configured to cover a part of the active region and a part of the junction termination layer, and a second metal layer configured to cover the first metal layer and the active region, wherein the first metal layer and the second metal layer contact the drift layer to provide a Schottky junction, and the first metal layer has a higher Schottky barrier height than the second metal layer.Type: ApplicationFiled: March 24, 2016Publication date: September 29, 2016Inventors: Kun Sik PARK, Jong II WON, Doo Hyung CHO
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Patent number: 9171621Abstract: A nonvolatile memory and a method of manufacturing a nonvolatile memory are disclosed. A nonvolatile memory according to an exemplary embodiment may include a deep well formed on a substrate, a first well formed within the deep well, a second well formed separately from the first well within the deep well, a first metal-oxide-semiconductor field-effect transistor (MOSFET) formed on the first well, and a second MOSFET formed on the second well. According to a method of manufacturing a nonvolatile memory according to an exemplary embodiment, a well region of a control MOSFET of a memory cell may be shared with a control MOSFET of an adjacent memory cell, or a well region of a tunneling MOSFET of a memory cell may be shared with a tunneling MOSFET of an adjacent memory cell, thereby reducing an area of the memory cells.Type: GrantFiled: April 26, 2013Date of Patent: October 27, 2015Assignee: Electronics and Telecommunications Research InstituteInventors: Kun Sik Park, Kyu Ha Baek
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Patent number: 8981937Abstract: An RFID tag includes: an antenna receiving an RF signal from a reader; an AFE (analog front end) generating voltage using the RF signal; and one or more switches interposed between the antenna and the AFE and controlling the connection between the antenna and the AFE through the switch operation.Type: GrantFiled: November 11, 2011Date of Patent: March 17, 2015Assignee: Electronics and Telecommunications Research InstituteInventors: Ji Man Park, Lee Mi Do, Kyu Ha Baek, Kun Sik Park, Dong Pyo Kim, Jong Chang Woo, Zin Sig Kim, Joo Yeon Kim, Ye Sul Jeong, Yong Hyun Ham
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Publication number: 20130294172Abstract: A nonvolatile memory and a method of manufacturing a nonvolatile memory are disclosed. A nonvolatile memory according to an exemplary embodiment may include a deep well formed on a substrate, a first well formed within the deep well, a second well formed separately from the first well within the deep well, a first metal-oxide-semiconductor field-effect transistor (MOSFET) formed on the first well, and a second MOSFET formed on the second well. According to a method of manufacturing a nonvolatile memory according to an exemplary embodiment, a well region of a control MOSFET of a memory cell may be shared with a control MOSFET of an adjacent memory cell, or a well region of a tunneling MOSFET of a memory cell may be shared with a tunneling MOSFET of an adjacent memory cell, thereby reducing an area of the memory cells.Type: ApplicationFiled: April 26, 2013Publication date: November 7, 2013Inventors: Kun Sik PARK, Kyu Ha BAEK
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Patent number: 8513655Abstract: An organic light emitting diode (OLED) and a method for manufacturing the same are provided. In the OLED, patterned metal electrodes are positioned on one or more of upper and lower portions of a light emission layer to allow light generated from the light emission layer to emit to an area between the patterned metal electrodes.Type: GrantFiled: December 21, 2010Date of Patent: August 20, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Lee Mi Do, Kun Sik Park, Ji Man Park, Dong Pyo Kim, Jin-Yeong Kang, Kyu Ha Baek
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Patent number: 8486830Abstract: A via forming method that includes forming via-holes in a substrate is provided. The method includes putting the substrate, having the via-holes, in a first solution to fill the via-holes with the first solution. Metal particles are sunk into the via-holes by supplying a second solution containing the metal particles to the first solution. A first curing process of heat-treating the substrate is performed so as to form vias in the via-holes. A multi-chip package that includes the substrate having the vias is also provided.Type: GrantFiled: July 13, 2010Date of Patent: July 16, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Dong Pyo Kim, Kyu Ha Baek, Kun Sik Park, Lee Mi Do
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Publication number: 20120161941Abstract: An RFID tag includes: an antenna receiving an RF signal from a reader; an AFE (analog front end) generating voltage using the RF signal; and one or more switches interposed between the antenna and the AFE and controlling the connection between the antenna and the AFE through the switch operation.Type: ApplicationFiled: November 11, 2011Publication date: June 28, 2012Applicant: Electronics and Telecommunications Research InstituteInventors: Ji Man PARK, Lee Mi DO, Kyu Ha BAEK, Kun Sik PARK, Dong Pyo KIM, Jong Chang WOO, Zin Sig KIM, Joo Yeon KIM, Ye Sul JEONG, Yong Hyun HAM
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Publication number: 20120057106Abstract: Provided are a polarizer and a liquid crystal display (LCD) in which wire grid polarizers are formed on a thin film transistor substrate and a color filter substrate, respectively, so that it is possible to reduce fabrication cost and the number of processes and decrease the thickness of the LCD. An LCD includes a thin film transistor substrate, a color filter substrate opposite to the thin film transistor substrate, and a liquid crystal layer positioned between the thin film transistor substrate and the color filter substrate. In the LCD, wire grid polarizing patterns are formed on the thin film transistor substrate and the color filter substrate, respectively.Type: ApplicationFiled: September 7, 2011Publication date: March 8, 2012Applicant: Electronics and Telecommunications Research InstituteInventors: Kun Sik PARK, Kyu Ha Baek, Lee Mi Do
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Patent number: 7994553Abstract: A complementary metal-oxide semiconductor (CMOS)-based planar type avalanche photo diode (APD) using a silicon epitaxial layer and a method of manufacturing the APD, the photo diode including: a substrate; a well layer of a first conductivity type formed in the substrate; an avalanche embedded junction formed in the well layer of the first conductivity type by low energy ion implantation; the silicon epitaxial layer formed in the avalanche embedded junction; a doping area of a second conductivity type opposite to the first conductive type, formed from a portion of a surface of the well layer of the first conductivity type in the avalanche embedded junction and forming a p-n junction; positive and negative electrodes formed on the doping area of the second conductivity type and the well layer of the first conductivity type separated from the doping area of the second conductivity type, respectively; and an oxide layer formed on an overall surface excluding a window where the positive and negative electrodes arType: GrantFiled: August 20, 2008Date of Patent: August 9, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Yong Sun Yoon, Kun Sik Park, Jong Moon Park, Bo Woo Kim, Jin Yeong Kang
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Publication number: 20110147468Abstract: Provided is a radio frequency identification (RFID) tag whose data can be stably read at a long distance on the basis of a passive RFID tag. The RFID tag includes a rechargeable unit charged to a predetermined voltage, and a power source including a direct current (DC) power source including a rectifier for converting an RF signal into DC power and a regulator for supplying a predetermined DC voltage, an interceptor disposed between the rechargeable unit and the DC power source to connecting or disconnecting the power to the rechargeable unit, and an overvoltage preventor connected to an output terminal of the DC power source in parallel.Type: ApplicationFiled: December 16, 2010Publication date: June 23, 2011Applicant: Electronics and Telecommunications Research InstituteInventors: Ji Man PARK, Lee Mi Do, Kyu Ha Baek, Kun Sik Park, Dong Pyo Kim