Patents by Inventor Kun-tack Lee

Kun-tack Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120085495
    Abstract: Provided herein are etching, cleaning and drying methods using a supercritical fluid, and a chamber system for conducting the same. The etching method includes etching the material layer using a supercritical carbon dioxide in which an etching chemical is dissolved, and removing an etching by-product created from a reaction between the material layer and the etching chemical using a supercritical carbon dioxide in which a cleaning chemical is dissolved. Methods of manufacturing a semiconductor device are also provided.
    Type: Application
    Filed: December 15, 2011
    Publication date: April 12, 2012
    Inventors: Hyo-San Lee, Chang-Ki Hong, Kun-Tack Lee, Woo-Gwan Shim, Jeong-Nam Han, Jung-Min Oh, Kwon-Tack Lim, Ha-Soo Hwang, Haldori Vuvaraj, Jae-Monk Jung
  • Publication number: 20120080061
    Abstract: Example embodiments relate to an apparatus for drying a substrate. The apparatus may include a housing including first barrier walls having a first height, a rotary chuck that is disposed within the housing and configured to rotate the substrate, a nozzle system that is disposed above the rotary chuck and configured to supply a fluid onto the substrate, a cleaning liquid supply unit supplying a cleaning liquid for cleaning the substrate to the nozzle system, and a drying liquid supply unit supplying a drying liquid for drying the substrate to the nozzle system.
    Type: Application
    Filed: September 23, 2011
    Publication date: April 5, 2012
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Young-Hoo Kim, Kun-Tack Lee, Seung-Yul Park, Yong-Bum Kwon
  • Publication number: 20120080059
    Abstract: Provided herein are etching, cleaning and drying methods using a supercritical fluid, and a chamber system for conducting the same. The etching method includes etching the material layer using a supercritical carbon dioxide in which an etching chemical is dissolved, and removing an etching by-product created from a reaction between the material layer and the etching chemical using a supercritical carbon dioxide in which a cleaning chemical is dissolved. Methods of manufacturing a semiconductor device are also provided.
    Type: Application
    Filed: December 15, 2011
    Publication date: April 5, 2012
    Inventors: Hyo-san Lee, Chang-Ki Hong, Kun-Tack Lee, Woo-Gwan Shim, Jeong-Nam Han, Jung-Min Oh, Kwon-Taek Lim, Ha-Soo Hwang, Haldural Yuvaraj, Jae-Mok Jung
  • Publication number: 20120083189
    Abstract: A pad conditioning disk, a pre-conditioning unit, and a CMP apparatus having the same are provided. The pad conditioning disk includes a base in which mountain-type tips and valley-type grooves are repeatedly connected to each other, and a cutting layer formed on the base layer. The cutting layer including conditioning particles deposited on surfaces of the tips and grooves. A surfaces roughness of conditioning particles deposited on the surfaces of the tips is less than a surface roughness of conditioning particles deposited on the surfaces of the grooves.
    Type: Application
    Filed: September 23, 2011
    Publication date: April 5, 2012
    Inventors: Jae-Kwang Choi, Hong-Jin Kim, Keon-Sik Seo, Sol Han, Kun-Tack Lee, Byoung-Ho Kwon
  • Publication number: 20120064727
    Abstract: Substrate treatment equipment includes a wet treatment apparatus for treating a substrate with a solution (liquid), a drying (treatment) apparatus discrete from the wet treatment apparatus and for drying the substrate using a supercritical fluid, and a transfer device. The substrate is extracted by the transfer device from the wet treatment apparatus after the substrate has been treated and the substrate is transferred by the device while wet to the dry treatment apparatus. To this end, various elements/methods may be used to keep the substrate wet or wet the substrate. In any case, the substrate is prevented from drying naturally, i.e., from air-drying, as the substrate is being transferred from the wet treatment apparatus to the drying apparatus. Thus, equipment and method prevent defects such as water spots and the leaning of fine structures on the substrate.
    Type: Application
    Filed: September 6, 2011
    Publication date: March 15, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-min Oh, Kun-tack Lee, Hyo-san Lee, Young-hoo Kim, Jung-won Lee, Sang-won Bae, Yong-jhin Cho
  • Publication number: 20120064680
    Abstract: A method of forming a capacitor structure and manufacturing a semiconductor device, the method of forming a capacitor structure including sequentially forming a first mold layer, a supporting layer, a second mold layer, an anti-bowing layer, and a third mold layer on a substrate having a conductive region thereon; partially removing the third mold layer, the anti-bowing layer, the second mold layer, the supporting layer, and the first mold layer to form a first opening exposing the conductive region; forming a lower electrode on a sidewall and bottom of the first opening, the lower electrode being electrically connected to the conductive region; further removing the third mold layer, the anti-bowing layer, and the second mold layer; partially removing the supporting layer to form a supporting layer pattern; removing the first mold layer; and sequentially forming a dielectric layer and upper electrode on the lower electrode and the supporting layer pattern.
    Type: Application
    Filed: September 9, 2011
    Publication date: March 15, 2012
    Inventors: Jung-Min Oh, Bo-Un Yoon, Gyu-Wan Choi, Kun-Tack Lee, Dae-Hyuk Kang, Im-Soo Park, Dong-Seok Lee, Young-Hoo Kim
  • Patent number: 8119476
    Abstract: In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: February 21, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Hyuk Kang, Bo-Un Yoon, Kun-Tack Lee, Woo-Gwan Shim, Ji-Hoon Cha, Im-Soo Park, Hyo-San Lee, Young-Hoo Kim, Jung-Min Oh
  • Patent number: 8110499
    Abstract: An insulation layer may be formed on an object having a contact region. The insulation layer may be partially etched to form an opening exposing the contact region. A material layer including silicon and oxygen may be formed on the exposed contact region. A metal layer may be formed on the material layer including silicon and oxygen. The material layer including silicon and oxygen may be reacted with the metal layer to form a metal oxide silicide layer at least on the contact region. A conductive layer may be formed on the metal oxide silicide layer to fill up the opening.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: February 7, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Hyuk Kang, Young-Hoo Kim, Chang-Ki Hong, Kun-Tack Lee, Jae-Dong Lee, Dae-Hong Eom, Jeong-Nam Han
  • Patent number: 8084367
    Abstract: Provided herein are etching, cleaning and drying methods using a supercritical fluid, and a chamber system for conducting the same. The etching method includes etching the material layer using a supercritical carbon dioxide in which an etching chemical is dissolved, and removing an etching by-product created from a reaction between the material layer and the etching chemical using a supercritical carbon dioxide in which a cleaning chemical is dissolved. Methods of manufacturing a semiconductor device are also provided.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: December 27, 2011
    Assignees: Samsung Electronics Co., Ltd, Pukyong National University
    Inventors: Hyo-san Lee, Chang-Ki Hong, Kun-Tack Lee, Woo-Gwan Shim, Jeong-Nam Han, Jung-Min Oh, Kwon-Taek Lim, Ha-Soo Hwang, Haldorai Yuvaraj, Jae-Mok Jung
  • Publication number: 20110306197
    Abstract: Method of manufacturing semiconductor device are provided including forming an insulation layer having a pad on a substrate; forming an etch stop layer on the insulation layer and the pad; forming a mold structure having at least one mold layer on the etch stop layer; forming a first supporting layer on the mold structure; etching the first supporting layer and the mold structure to form a first opening exposing the etch stop layer; forming a spacer on a sidewall of the first opening; etching the etch stop layer using the spacer as an etching mask to form a second opening, different from the first opening, exposing a first portion of the pad having a first associated area; etching the etch stop layer using the spacer as an etching mask to form a third opening exposing a second portion of the pad having a second associated area, the second associated area being larger than the first associated area; and etching the mold structure to form a fourth opening having a width larger than a width of the third opening.
    Type: Application
    Filed: June 9, 2011
    Publication date: December 15, 2011
    Inventors: Young-Hoo Kim, Bo-Un Yoon, Kun-Tack Lee, Dae-Hyuk Kang, Im-Soo Park
  • Publication number: 20110306208
    Abstract: Methods for forming a mold for a storage electrode in a semiconductor device include forming an interlayer dielectric layer including a contact plug on a substrate. A first mold dielectric layer is formed of a first material on the interlayer dielectric layer. A second mold dielectric layer is formed of a second material on the first mold dielectric layer. The second material has a different etch selectivity than the first material. A first opening is formed that penetrates the first and second mold dielectric layers. The first opening is dry etched to define a second opening having a larger width in the first mold dielectric layer than in the second mold dielectric layer based on the different etch selectivity of the first and second mold dielectric layers to define the mold for the storage electrode.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 15, 2011
    Inventors: Jung-Won Lee, Dae-Hyuk Kang, Bo-Un Yoon, Kun-Tack Lee
  • Publication number: 20110287625
    Abstract: A method of forming a pattern in a semiconductor device includes forming an etching object layer on a substrate, the etching object layer is an oxide that is substantially free of impurities. A mask is formed on the etching object layer, the mask is an oxide that includes impurities. The etching object layer is patterned using the mask as an etching mask and then the mask is removed. The mask is removed using an etchant having an etching selectivity to an oxide that is substantially free of impurities and an oxide that includes impurities during removing of the mask to limit damage to the patterned etching object layer during removal of the mask.
    Type: Application
    Filed: April 4, 2011
    Publication date: November 24, 2011
    Inventors: Dae-Hyuk Kang, Kun-Tack Lee, Dae-Hong Eom, Bo-Un Yoon, Jeong-Nam Han
  • Publication number: 20110281415
    Abstract: In a method of forming an isolation layer, first and second trenches are formed on a substrate. The first and the second trenches have first and second widths, respectively, and the second width is greater than the first width. A second isolation layer pattern partially fills the second trench. A first isolation layer pattern and the third isolation layer pattern are formed. The first isolation layer pattern fills the first trench, and the third isolation layer pattern is formed on the second isolation layer pattern and fills a remaining portion of the second trench.
    Type: Application
    Filed: May 17, 2011
    Publication date: November 17, 2011
    Inventors: Dae-Hyuk KANG, Jung-Won Lee, Bo-Un Yoon, Kun-Tack Lee
  • Publication number: 20110217833
    Abstract: In an etchant for etching a capping layer having etching selectivity with respect to a dielectric layer, the capping layer changes compositions of the dielectric layer, to thereby control a threshold voltage of a gate electrode including the dielectric layer. The etchant includes about 0.01 to 3 percent by weight of an acid, about 10 to 40 percent by weight of a fluoride salt and a solvent. Accordingly, the dielectric layer is prevented from being damaged by the etching process for removing the capping layer and the electric characteristics of the gate electrode are improved.
    Type: Application
    Filed: March 4, 2011
    Publication date: September 8, 2011
    Inventors: Hyo-San Lee, Bo-Un Yoon, Kun-Tack Lee, Hag-Ju Cho, Sang-Jin Hyun, Hoon-Joo Na, Hyung-Seok Hong
  • Publication number: 20110201203
    Abstract: In a method of forming a hole, an insulation layer is formed on a substrate, and a preliminary hole exposing the substrate is formed through the insulation layer. A photosensitive layer pattern including an organic polymer is then formed on the substrate to fill the preliminary hole. An etching gas including hydrogen fluoride (HF) or fluorine (F2) is then provided onto the photosensitive layer pattern to etch the insulation layer so that width of the preliminary hole is increased.
    Type: Application
    Filed: February 11, 2011
    Publication date: August 18, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyo-San Lee, Bo-Un Yoon, Kun-Tack Lee, Dae-Hyuk Kang, Seong-Ho Moon, So-Ra Han
  • Publication number: 20110159660
    Abstract: In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.
    Type: Application
    Filed: October 18, 2010
    Publication date: June 30, 2011
    Inventors: Dae-Hyuk Kang, Bo-Un Yoon, Kun-Tack Lee, Woo-Gwan Shim, Ji-Hoon Cha, Im-Soo Park, Hyo-San Lee, Young-Hoo Kim, Jung-Min Oh
  • Patent number: 7959738
    Abstract: A method of removing a photoresist may include permeating supercritical carbon dioxide into the photoresist on a substrate having a conductive structure including a metal. The photoresist permeating the supercritical carbon dioxide may be easily removable. The photoresist permeating the supercritical carbon dioxide may be removed using a photoresist cleaning solution from the substrate. The photoresist cleaning solution may include an alkanolamine solution of about 8 percent by weight to about 20 percent by weight, a polar organic solution of about 25 percent by weight to about 40 percent by weight, a reducing agent of about 0.5 percent by weight to about 3 percent by weight with the remainder being water. The photoresist may be easily removed without damaging the conductive structure in a plasma process.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: June 14, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Hyuk Kang, Hyo-San Lee, Dong-Gyun Han, Chang-Ki Hong, Kun-Tack Lee
  • Publication number: 20110083807
    Abstract: Provided are an apparatus and method for treating wafers using a supercritical fluid. The wafer treatment apparatus includes a plurality of chambers; a first supply supplying a first fluid in a supercritical state; a second supply supplying a mixture of the first fluid and a second fluid; a plurality of first and second valves; and a controller selecting a first chamber of the plurality of chambers for wafer treatment to control the open/closed state of each of the plurality of first valves so that the first fluid can be supplied only to the first chamber of the plurality of chambers and selecting a second chamber of the plurality of chambers to control the open/closed state of each of the plurality of second valves so that the mixture of the first fluid and a second fluid can be supplied only to the second chamber of the plurality of chambers.
    Type: Application
    Filed: December 21, 2010
    Publication date: April 14, 2011
    Inventors: Hyo-san Lee, Chang-ki Hong, Kun-tack Lee, Jeong-nam Han
  • Publication number: 20110073866
    Abstract: In a vertical-type non-volatile memory device, an insulation layer pattern is provided on a substrate, the insulation layer pattern having a linear shape. Single-crystalline semiconductor patterns are provided on the substrate to make contact with both sidewalls of the insulation layer pattern, the single-crystalline semiconductor patterns having a pillar shape that extends in a vertical direction relative to the substrate. A tunnel oxide layer is provided on the single-crystalline semiconductor pattern. A lower electrode layer pattern is provided on the tunnel oxide layer and on the substrate. A plurality of insulation interlayer patterns is provided on the lower electrode layer pattern, the insulation interlayer patterns being spaced apart from one another by a predetermined distance along the single-crystalline semiconductor pattern. A charge-trapping layer and a blocking dielectric layer are sequentially formed on the tunnel oxide layer between the insulation interlayer patterns.
    Type: Application
    Filed: August 31, 2010
    Publication date: March 31, 2011
    Inventors: Young-Hoo Kim, Hyo-San Lee, Sang-Won Bae, Bo-Un Yoon, Kun-Tack Lee
  • Patent number: 7857939
    Abstract: Provided are an apparatus and method for treating wafers using a supercritical fluid. The wafer treatment apparatus includes a plurality of chambers; a first supply supplying a first fluid in a supercritical state; a second supply supplying a mixture of the first fluid and a second fluid; a plurality of first and second valves; and a controller selecting a first chamber of the plurality of chambers for wafer treatment to control the open/closed state of each of the plurality of first valves so that the first fluid can be supplied only to the first chamber of the plurality of chambers and selecting a second chamber of the plurality of chambers to control the open/closed state of each of the plurality of second valves so that the mixture of the first fluid and a second fluid can be supplied only to the second chamber of the plurality of chambers.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: December 28, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo-san Lee, Chang-ki Hong, Kun-tack Lee, Jeong-nam Han