Patents by Inventor Kun Tian

Kun Tian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180307533
    Abstract: A mechanism is described for facilitating multi-level scheduling of workloads in computing devices. A method of embodiments, as described herein, includes facilitating multiple levels of scheduling for processing of workloads using multiple levels of queues, where the workloads are associated with a device including a processor of a computing device.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Inventors: Kun Tian, David J. Cowperthwaite, Murali Ramadoss, Balaji Vembu, Zhi Wang, Eric C. Samson, Altug Koker, Abhishek R. Appu, Joydeep Ray
  • Publication number: 20180308209
    Abstract: Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for an apparatus comprising a thread dispatcher to dispatch a thread for execution; a compute unit having a single instruction, multiple thread architecture, the compute unit to execute multiple concurrent threads; and a memory coupled with the compute unit, the memory to store thread state for a suspended thread, wherein the compute unit is to: detect that all threads on the compute unit are blocked from execution, select a victim thread from the multiple concurrent threads, suspend the victim thread, store thread state of the victim thread to the memory, and replace the victim thread with an additional thread to be executed.
    Type: Application
    Filed: June 18, 2018
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Murali Ramadoss, Balaji Vembu, Eric C. Samson, Kun Tian, David J. Cowperthwaite, Altug Koker, Zhi Wang, Joydeep Ray, Subramaniam M. Maiyuran, Abhishek R. Appu
  • Publication number: 20180300845
    Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.
    Type: Application
    Filed: April 17, 2017
    Publication date: October 18, 2018
    Applicant: Intel Corporation
    Inventors: Adam T. Lake, Guei-Yuan Lueh, Balaji Vembu, Murali Ramadoss, Prasoonkumar Surti, Abhishek R. Appu, Altug Koker, Subramaniam M. Maiyuran, Eric C. Samson, David J. Cowperthwaite, Zhi Wang, Kun Tian, David Puffer, Brian T. Lewis
  • Publication number: 20180293183
    Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.
    Type: Application
    Filed: April 7, 2017
    Publication date: October 11, 2018
    Inventors: NIRANJAN L. COORAY, ABHISHEK R. APPU, ALTUG KOKER, JOYDEEP RAY, BALAJI VEMBU, PATTABHIRAMAN K, DAVID PUFFER, DAVID J. COWPERTHWAITE, RAJESH M. SANKARAN, SATYESHWAR SINGH, SAMEER KP, ANKUR N. SHAH, KUN TIAN
  • Publication number: 20180293700
    Abstract: Systems and methods for container access to graphics processing unit (GPU) resources are disclosed herein. In some embodiments, a computing system may include a physical GPU and kernel-mode driver circuitry, to communicatively couple with the physical GPU to create a plurality of emulated GPUs and a corresponding plurality of device nodes. Each device node may be associated with a single corresponding user-side container to enable communication between the user-side container and the corresponding emulated GPU. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: May 29, 2015
    Publication date: October 11, 2018
    Inventors: Kun TIAN, Yao Zu DONG, Zhiyuan LV
  • Publication number: 20180292897
    Abstract: One embodiment of a virtual reality apparatus comprises: a graphics processing engine comprising a plurality of graphics processing stages, the graphics processing engine to render a plurality of image frames for left and right displays of a head mounted display (HMD); and foveation control hardware logic to independently control two or more of the plurality of graphics processing stages based on feedback received from an eye tracking module of the HMD, the feedback indicating a foveated region selected based on a current or anticipated direction of a user's gaze, the foveation control hardware logic to cause the two or more of the graphics processing stages to process the foveated region differently than other regions of the image frames.
    Type: Application
    Filed: April 7, 2017
    Publication date: October 11, 2018
    Inventors: INGO WALD, BRENT E. INSKO, PRASOONKUMAR SURTI, KUN TIAN, ADAM T. LAKE, YAO ZU EDDIE DONG, PETER L. DOYLE
  • Patent number: 10043232
    Abstract: One embodiment provides for a general-purpose graphics processing unit comprising a compute cluster including multiple compute units, a stall notification module to detect that one or more compute units in the compute cluster are stalled and send stall notification, and a rebalance module to receive the stall notification, the rebalance module to migrate a first workload from one or more stalled compute units in response to the stall notification.
    Type: Grant
    Filed: April 9, 2017
    Date of Patent: August 7, 2018
    Assignee: Intel Corporation
    Inventors: Murali Ramadoss, Balaji Vembu, Eric C. Samson, Kun Tian, David J. Cowperthwaite, Altug Koker, Zhi Wang, Joydeep Ray, Subramaniam M. Maiyuran, Abhishek R. Appu
  • Publication number: 20180210840
    Abstract: An apparatus and method are described for managing a virtual graphics processor unit (GPU). For example, one embodiment of an apparatus comprises: a dynamic addressing module to map portions of an address space required by the virtual machine to matching free address spaces of a host if such matching free address spaces are available, and to select non-matching address spaces for those portions of the address space required by the virtual machine which cannot be matched with free address spaces of the host; and a balloon module to perform address space ballooning (ASB) techniques for those portions of the address space required by the virtual machine which have been mapped to matching address spaces of the host; and address remapping logic to perform address remapping techniques for those portions of the address space required by the virtual machine which have not been mapped to matching address spaces of the host.
    Type: Application
    Filed: November 16, 2017
    Publication date: July 26, 2018
    Inventors: Yao Zu DONG, Kun TIAN
  • Publication number: 20180167364
    Abstract: An apparatus, system, method, and machine-readable medium are disclosed. In one embodiment the apparatus is a network interface controller that includes one virtual function owned by a virtual machine present in the computer system. The controller includes a simple filtering agent that is associated with the first virtual function. The agent enforces simple filter rules for received network packets. The simple filter rules are capable of blocking the network packets from reaching the virtual machine. The apparatus also includes another virtual function that is owned by a virtual machine monitor present in the computer system. The controller also includes a side bounce filtering agent to forward the first network packet to the second virtual function if the first packet is blocked by the at least one of the one or more simple filter rules.
    Type: Application
    Filed: August 15, 2017
    Publication date: June 14, 2018
    Inventors: Yaozu Dong, Kun Tian
  • Publication number: 20180165791
    Abstract: An apparatus and method are described for performing virtualization using virtual machine (VM) sets. For example, one embodiment of an apparatus comprises: graphics processing unit (GPU) to process graphics commands and responsively render a plurality of image frames; a hypervisor to virtualize the GPU to share the GPU among a plurality of virtual machines (VMs); and VM set management logic to establish a plurality of VM sets, each set comprising a plurality of VMs, the VM set management logic to partition graphics memory address (GMADR) space across each of the VM sets but to share the GMADR space between VMs within each VM set.
    Type: Application
    Filed: June 26, 2015
    Publication date: June 14, 2018
    Inventors: Yao Zu DONG, Kun TIAN
  • Publication number: 20180157517
    Abstract: Examples may include techniques to run one or more containers on a virtual machine (VM). Examples include cloning a first VM to result in a second VM. The cloned first VM may run at least a set of containers capable of separately executing one or more applications. In some examples, some cloned containers are stopped at either the first or second VMs to allow for at least some resources provisioned to support the first or second VMs to be reused or recycled at a hosting node. In other examples, the second VM is migrated from the hosting node to a destination hosting node to further enable resources to be reused or recycled at the hosting node.
    Type: Application
    Filed: June 26, 2015
    Publication date: June 7, 2018
    Applicant: Intel Corporation
    Inventors: Yao Zu Dong, Kun Tian
  • Publication number: 20180143885
    Abstract: It includes techniques to provide for reliable primary and secondary containers arranged to separately execute an application that receives request packets for processing by the application. The request packets may be received from a client coupled with a server arranged to host the primary container or the secondary container. The client coupled with the server through a network. Coarse-grained lock-stepping (COLO) methods may be utilized to facilitate in providing the reliable primary and secondary containers.
    Type: Application
    Filed: June 25, 2015
    Publication date: May 24, 2018
    Applicant: Intel Corporation
    Inventors: YAO ZU DONG, YUNHONG JIANG, KUN TIAN
  • Publication number: 20180136971
    Abstract: Examples may include techniques for virtual machine (VM) migration. Examples may include selecting a VM for live migration from a source node to a destination node, predicting a time period associated with the live migration, and selecting another VM from which allocated source node bandwidth may borrowed to facilitate the live migration within the predicted time.
    Type: Application
    Filed: June 26, 2015
    Publication date: May 17, 2018
    Applicant: Intel Corporation
    Inventors: YAO ZU DONG, KUN TIAN
  • Publication number: 20180130936
    Abstract: A thermoelectric material, having a formula TbxM1y-xM2zOw where M1 is one of Ca, Mg, Sr, Ba and Ra, M2 is at least one of Co, Fe, Ni, and Mn, x ranges from 0.01 to 5; y is 1, 2, 3, or 5; z is 1, 2, 3, or 4; and w is 1, 2, 3, 4, 5, 7, 8, 9, or 14. The thermoelectric material is chemically stable within 5% for one year and is also non-toxic. The thermoelectric material can also be incorporated into a thermoelectric system which can be used to generate electricity from waste heat sources or to cool an adjacent region.
    Type: Application
    Filed: August 7, 2017
    Publication date: May 10, 2018
    Inventors: Ashutosh Tiwari, Shrikant Saini, Kun Tian, Haritha Sree Yaddanapudi, Yinong Yin
  • Publication number: 20180107605
    Abstract: Apparatuses, methods and storage medium associated with computing that include usage and backup of persistent memory are disclosed herein. In embodiments, an apparatus for computing may comprise one or more processors and persistent memory to host operation of one or more virtual machines; and one or more page tables to store a plurality of mappings to map a plurality of virtual memory pages of a virtualization of the persistent memory of the one or more virtual machines to a plurality of physical memory pages of the persistent memory allocated to the one or more virtual machines. The apparatus may further include a memory manager to manage accesses of the persistent memory that includes a copy-on-write mechanism to service write instructions that address virtual memory pages mapped to physical memory pages that are marked as read-only. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 17, 2015
    Publication date: April 19, 2018
    Inventors: Yao Zu DONG, Kun TIAN
  • Patent number: 9921868
    Abstract: Generally, this disclosure describes systems (and methods) of moderating interrupts in a virtualization environment. An overflow interval is defined. The overflow interrupt interval is used to trigger activation of an inactive guest so that the guest may respond to a critical event. The guest, including a network application, may be active for a first time interval and inactive for a second time interval. A latency interrupt interval may be defined. The latency interrupt interval is configured for interrupt moderation when the network application associated with a packet flow is active, i.e., when the guest including the network application is active on a processor. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: March 20, 2018
    Assignee: INTEL CORPORATION
    Inventors: Yao Zu Dong, Yunhong Jiang, Kun Tian
  • Publication number: 20180033116
    Abstract: An apparatus and method are described for a software agnostic multi-GPU implementation. For example, one embodiment of an apparatus comprises: a plurality of physical graphics processor units (pGPUs) to execute graphics commands; a graphics driver to receive graphics commands generated from applications via a graphics application programming interface (API); a mediator to receive commands directed to pGPU resources from the graphics driver, the mediator to map the plurality of pGPUs into a virtual graphics processor unit (vGPU) visible to the graphics driver, the mediator further including a load balancer to distribute commands received by the vGPU to each of the plurality of pGPUs in accordance with a load balancing policy.
    Type: Application
    Filed: March 18, 2015
    Publication date: February 1, 2018
    Inventors: Kun TIAN, David J. COWPERTHWAITE
  • Patent number: 9824026
    Abstract: An apparatus and method are described for managing a virtual graphics processor unit (GPU). For example, one embodiment of an apparatus comprises: a dynamic addressing module to map portions of an address space required by the virtual machine to matching free address spaces of a host if such matching free address spaces are available, and to select non-matching address spaces for those portions of the address space required by the virtual machine which cannot be matched with free address spaces of the host; and a balloon module to perform address space ballooning (ASB) techniques for those portions of the address space required by the virtual machine which have been mapped to matching address spaces of the host; and address remapping logic to perform address remapping techniques for those portions of the address space required by the virtual machine which have not been mapped to matching address spaces of the host.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventors: Yao Zu Dong, Kun Tian
  • Publication number: 20170329623
    Abstract: Methods, software, and apparatus for application transparent, high available GPU computing with VM checkpointing. The guest access of certain GPU resources, such as MMIO resources, are trapped to keep a copy of guest context per semantics, and/or emulate the guest access of the resources prior to submission to the GPU, while other commands relating to certain graphics memory address regions are trapped before being passed through to the GPU. The trapped commands are scanned before submission to predict: a) potential to-be-dirtied graphics memory pages, and b) the execution time of intercepted commands, so the next checkpointing can be aligned to a predicted execution time. The GPU internal states are drained by flushing internal context/tlb/cache, at the completion of submitted commands, and then a snapshot of the vGPU state is taken, based on tracked GPU state, GPU context (through GPU-specific commands), detected dirty graphics memory pages and predicted to-be dirtied graphics memory pages.
    Type: Application
    Filed: November 24, 2014
    Publication date: November 16, 2017
    Inventors: Yaozu Dong, Kun Tian
  • Publication number: 20170300347
    Abstract: Examples may include a determining a checkpointing/delivery policy for primary and secondary virtual machines based on output-packet-similarities. The output-packet-similarities may be based on a comparison of time intervals via which content matched for packets outputted from the primary and secondary virtual machines. A checkpointing/delivery mode may then be selected based, at least in part, on the determined checkpointing/delivery policy.
    Type: Application
    Filed: October 8, 2014
    Publication date: October 19, 2017
    Applicant: INTEL CORPORATION
    Inventors: KUN TIAN, YAO ZU DONG