Patents by Inventor Kun-Yung K. Chang
Kun-Yung K. Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8040988Abstract: An integrated circuit device having a selectable data rate clock data recovery (CDR) circuit and a selectable data rate transmit circuit. The CDR circuit includes a receive circuit to capture a plurality of samples of an input signal during a cycle of a first clock signal. A select circuit is coupled to the receive circuit to select, according to a receive data rate select signal, one of the plurality of samples to be a first selected sample of the input signal and another of the plurality of samples to be a second selected sample of the input signal. A phase control circuit is coupled to receive the first and second selected samples of the input signal and includes circuitry to compare the selected samples to determine whether the first clock signal leads or lags a transition of the input signal. The transmit circuit includes a serializing circuit to receive a parallel set of bits and to output the set of bits in sequence to an output driver in response to a first clock signal.Type: GrantFiled: March 12, 2007Date of Patent: October 18, 2011Assignee: Rambus, Inc.Inventors: Kun-Yung K. Chang, Kevin S. Donnelly
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Patent number: 7467320Abstract: A fault-tolerant clock generation circuit. First and second clock signal generators are provided to generate first and second clock signals. The second clock signal generator includes a locked loop circuit that, in a first operating mode, adjusts the phase of the second clock signal as necessary to maintain phase alignment between the first and second clock signals. A fail detect circuit is provided to determine whether a failure relating to generation of the first clock signal has occurred and, if so, to assert a hold signal. The locked loop circuit responds to assertion of the hold signal by transitioning to a second operating mode in which the phase of the second clock signal is not adjusted.Type: GrantFiled: July 10, 2006Date of Patent: December 16, 2008Assignee: Rambus Inc.Inventors: Kun-Yung K. Chang, Mark A. Horowitz
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Patent number: 7190754Abstract: An integrated circuit device having a selectable data rate clock data recovery (CDR) circuit and a selectable data rate transmit circuit. The CDR circuit includes a receive circuit to capture a plurality of samples of an input signal during a cycle of a first clock signal. A select circuit is coupled to the receive circuit to select, according to a receive data rate select signal, one of the plurality of samples to be a first selected sample of the input signal and another of the plurality of samples to be a second selected sample of the input signal. A phase control circuit is coupled to receive the first and second selected samples of the input signal and includes circuitry to compare the selected samples to determine whether the first clock signal leads or lags a transition of the input signal. The transmit circuit includes a serializing circuit to receive a parallel set of bits and to output the set of bits in sequence to an output driver in response to a first clock signal.Type: GrantFiled: December 24, 2001Date of Patent: March 13, 2007Assignee: Rambus Inc.Inventors: Kun-Yung K. Chang, Kevin S. Donnelly
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Patent number: 7099424Abstract: A clock data recovery (CDR) circuit to recover a clock signal and data signal from an input signal. The CDR circuit includes a control circuit, a select circuit and a phase adjust circuit. The control circuit generates a first control signal according to a phase relationship between the input signal and a first clock signal. The select circuit is coupled to receive the first control signal from the control circuit and coupled to receive a second control signal. The select circuit is responsive to a select signal to select either the first control signal or the second control signal to be output as a selected control signal. The phase adjust circuit is coupled to receive the selected control signal from the select circuit, the phase adjust circuit being responsive to the selected control signal to adjust the phase of the first clock signal.Type: GrantFiled: August 28, 2001Date of Patent: August 29, 2006Assignee: Rambus Inc.Inventors: Kun-Yung K. Chang, Jason C. Wei, Donald V. Perino
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Patent number: 7089442Abstract: A fault-tolerant clock generation circuit. First and second clock signal generators are provided to generate first and second clock signals. The second clock signal generator includes a locked loop circuit that, in a first operating mode, adjusts the phase of the second clock signal as necessary to maintain phase alignment between the first and second clock signals. A fail detect circuit is provided to determine whether a failure relating to generation of the first clock signal has occurred and, if so, to assert a hold signal. The locked loop circuit responds to assertion of the hold signal by transitioning to a second operating mode in which the phase of the second clock signal is not adjusted.Type: GrantFiled: April 30, 2003Date of Patent: August 8, 2006Assignee: Rambus Inc.Inventors: Kun-Yung K. Chang, Mark A. Horowitz
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Publication number: 20040158759Abstract: A fault-tolerant clock generation circuit. First and second clock signal generators are provided to generate first and second clock signals. The second clock signal generator includes a locked loop circuit that, in a first operating mode, adjusts the phase of the second clock signal as necessary to maintain phase alignment between the first and second clock signals. A fail detect circuit is provided to determine whether a failure relating to generation of the first clock signal has occurred and, if so, to assert a hold signal. The locked loop circuit responds to assertion of the hold signal by transitioning to a second operating mode in which the phase of the second clock signal is not adjusted.Type: ApplicationFiled: April 30, 2003Publication date: August 12, 2004Inventors: Kun-Yung K. Chang, Mark A. Horowitz
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Patent number: 6696829Abstract: An integrated circuit device having a self-resetting phase-locked loop (PLL) circuit. The PLL circuit generates an output clock signal having a first frequency in a first operating mode and a second frequency in a second operating mode, the second frequency being determined, at least in part, by a reference clock signal. A control circuit within the integrated circuit resets the PLL circuit by selecting the first operating mode for a predetermined time interval, then selecting the second operating mode.Type: GrantFiled: November 16, 2001Date of Patent: February 24, 2004Assignee: Rambus Inc.Inventors: Nhat M. Nguyen, Kun-Yung K. Chang