Patents by Inventor Kunihiko Nishi

Kunihiko Nishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8937390
    Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: January 20, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Nae Hisano, Shigeo Ohashi, Yasuo Osone, Yasuhiro Naka, Hiroyuki Tenmei, Kunihiko Nishi, Hiroaki Ikeda, Masakazu Ishino, Hideharu Miyake, Shiro Uchiyama
  • Publication number: 20140183730
    Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.
    Type: Application
    Filed: March 6, 2014
    Publication date: July 3, 2014
    Inventors: Nae HISANO, Shigeo OHASHI, Yasuo OSONE, Yasuhiro NAKA, Hiroyuki TENMEI, Kunihiko NISHI, Hiroaki IKEDA, Masakazu ISHINO, Hideharu MIYAKE, Shiro UCHIYAMA
  • Patent number: 8704352
    Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: April 22, 2014
    Inventors: Nae Hisano, Shigeo Ohashi, Yasuo Osone, Yasuhiro Naka, Hiroyuki Tenmei, Kunihiko Nishi, Hiroaki Ikeda, Masakazu Ishino, Hideharu Miyake, Shiro Uchiyama
  • Patent number: 8334465
    Abstract: A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusion 20 which is provided in low melting point metal 15 for electrically connecting mutually joined wafers 61 and 62, and which defines an interval between mutually joined wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted. A joining structure of wafers 61 and 62 is manufactured by using wafers 61 and 62, at least one of which has protrusion 20. In the manufactured joining structure of wafers 61 and 62, wafers 61 and 62 are electrically connected to each other by low melting point metal 15, and protrusion 20, which defines the interval between wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted, is provided in low melting point metal 15.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: December 18, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Masakazu Ishino, Hiroaki Ikeda, Hideharu Miyake, Shiro Uchiyama, Hiroyuki Tenmei, Kunihiko Nishi, Yasuhiro Naka, Nae Hisano
  • Patent number: 7754581
    Abstract: A method for manufacturing a semiconductor device includes the steps of forming first and second semiconductor wafers each including an array of chips and elongate electrodes, forming a groove on scribe lines separating the chips from one another; coating a surface of one of the semiconductor wafers with adhesive; bonding together the semiconductor wafers while allowing the groove to receive therein excessive adhesive; and heating the wafers to connect the elongate electrodes of both the semiconductor wafers.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: July 13, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroaki Ikeda, Masakazu Ishino, Hiroyuki Tenmei, Naoya Kanda, Yasuhiro Naka, Kunihiko Nishi
  • Publication number: 20100171213
    Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.
    Type: Application
    Filed: January 6, 2010
    Publication date: July 8, 2010
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Nae HISANO, Shigeo OHASHI, Yasuo OSONE, Yasuhiro NAKA, Hiroyuki TENMEI, Kunihiko NISHI, Hiroaki IKEDA, Masakazu ISHINO, Hideharu MIYAKE, Shiro UCHIYAMA
  • Patent number: 7678706
    Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: March 16, 2010
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
  • Patent number: 7618847
    Abstract: A bonding method (three-dimensional mounting) of semiconductor substrates is provided to sequentially bond a principal surface of a silicon wafer on which coupling bumps are formed, and a principal surface of the other silicon wafer on which pads are formed, by an adhesive applied to at least one of the principal surfaces. However, there is a problem of poor electrical coupling due to displacement of the bumps and the pads when bonded together. The present invention solves such a problem by conducting temporary positioning of the silicon wafers, adjusting the positions of the coupling bumps and pads while confirming the positions by a method such as x-ray capable of passing through the silicon wafers, and bonding the bumps and the pads together while hardening an interlayer adhesive provided between the principal surfaces of the silicon wafers by thermocompression.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: November 17, 2009
    Assignees: Elpida Memory, Inc., Hitachi, Ltd.
    Inventors: Hiroyuki Tenmei, Kunihiko Nishi, Yasuhiro Naka, Nae Hisano, Hiroaki Ikeda, Masakazu Ishino
  • Patent number: 7541667
    Abstract: A manufacturing method of a semiconductor device including preparing a lead frame having a die pad, leads arranged around the die pad and a silver plating layer formed over a first portion of each of the leads, mounting a semiconductor chip over a main surface of the die pad with a rear surface of the chip fixed to the main surface of the die pad, electrically connecting electrodes of the chip with the leads through wires, forming a molding resin sealing the die pad, the first portion, the semiconductor chip, and the wires, and forming a lead-free solder plating layer over a second portion of each of the leads exposed from the molding resin. An area of the die pad is smaller than an area of the chip, and a part of the molding resin contacts with the rear surface of the chip exposed from the die pad.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: June 2, 2009
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Kunihiko Nishi
  • Publication number: 20090134498
    Abstract: The present invention includes a semiconductor element provided with an electrode passing through front and back sides. The electrode is formed as a cylinder including a hollow portion, and stress relaxing material is provided in the hollow portion, which is used to reduce stress that is induced between the semiconductor element and the electrode. The stress relaxing material is an elastic body made of resin material.
    Type: Application
    Filed: November 19, 2008
    Publication date: May 28, 2009
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Hiroaki IKEDA, Masakazu Ishino, Hideharu Miyake, Shiro Uchiyama, Yasuhiro Naka, Nae Hisano, Hisashi Tanie, Kunihiko Nishi, Hiroyuki Tenmei
  • Patent number: 7528014
    Abstract: A manufacturing method of a semiconductor device including preparing a lead frame having a die pad, leads arranged around the die pad and a silver plating layer formed over a first portion of each of the leads, mounting a semiconductor chip over a main surface of the die pad with a rear surface of the chip fixed to the main surface of the die pad, electrically connecting electrodes of the chip with the leads through wires, forming a molding resin sealing the die pad, the first portion, the semiconductor chip, and the wires, and forming a lead-free solder plating layer over a second portion of each of the leads exposed from the molding resin. An area of the die pad is smaller than an area of the chip, and a part of the molding resin contacts with the rear surface of the chip exposed from the die pad.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: May 5, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Kunihiko Nishi
  • Publication number: 20090109641
    Abstract: A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusion 20 which is provided in low melting point metal 15 for electrically connecting mutually joined wafers 61 and 62, and which defines an interval between mutually joined wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted. A joining structure of wafers 61 and 62 is manufactured by using wafers 61 and 62, at least one of which has protrusion 20. In the manufactured joining structure of wafers 61 and 62, wafers 61 and 62 are electrically connected to each other by low melting point metal 15, and protrusion 20, which defines the interval between wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted, is provided in low melting point metal 15.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 30, 2009
    Applicant: Elpida Memory, Inc.
    Inventors: Masakazu Ishino, Hiroaki Ikeda, Hideharu Miyake, Shiro Uchiyama, Hiroyuki Tenmei, Kunihiko Nishi, Yasuhiro Naka, Nae Hisano
  • Publication number: 20090072414
    Abstract: A bonding method (three-dimensional mounting) of semiconductor substrates is provided to sequentially bond a principal surface of a silicon wafer on which coupling bumps are formed, and a principal surface of the other silicon wafer on which pads are formed, by an adhesive applied to at least one of the principal surfaces. However, there is a problem of poor electrical coupling due to displacement of the bumps and the pads when bonded together. The present invention solves such a problem by conducting temporary positioning of the silicon wafers, adjusting the positions of the coupling bumps and pads while confirming the positions by a method such as x-ray capable of passing through the silicon wafers, and bonding the bumps and the pads together while hardening an interlayer adhesive provided between the principal surfaces of the silicon wafers by thermocompression.
    Type: Application
    Filed: August 7, 2008
    Publication date: March 19, 2009
    Inventors: Hiroyuki TENMEI, Kunihiko NISHI, Yasuhiro NAKA, Nae HISANO, Hiroaki IKEDA, Masakazu ISHINO
  • Patent number: 7420284
    Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: September 2, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masnori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
  • Patent number: RE41478
    Abstract: A semiconductor device comprising a semiconductor pellet mounted on a pellet mounting area of the main surface of a base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to bonding pads arranged on the main surface of the semiconductor pellet. The base substrate is formed of a rigid substrate, and its first electrode pads are electrically connected to the second electrode pads arranged on its reverse side. The semiconductor pellet is mounted on the pellet mounting area of the main surface of the base substrate, with its main surface downward, and its bonding pads are connected electrically with the second electrode pads of the base substrate through bonding wires passing through slits formed in the base substrate.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: August 10, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Atsushi Nakamura, Kunihiko Nishi
  • Patent number: RE41721
    Abstract: A semiconductor device comprising a semiconductor pellet mounted on a pellet mounting area of the main surface of a base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to bonding pads arranged on the main surface of the semiconductor pellet. The base substrate is formed of a rigid substrate, and its first electrode pads are electrically connected to the second electrode pads arranged on its reverse side. The semiconductor pellet is mounted on the pellet mounting area of the main surface of the base substrate, with its main surface downward, and its bonding pads are connected electrically with the second electrode pads of the base substrate through bonding wires passing through slits formed in the base substrate.
    Type: Grant
    Filed: July 7, 2000
    Date of Patent: September 21, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Atsushi Nakamura, Kunihiko Nishi
  • Patent number: RE41722
    Abstract: A semiconductor device comprising a semiconductor pellet mounted on a pellet mounting area of the main surface of a base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to bonding pads arranged on the main surface of the semiconductor pellet. The base substrate is formed of a rigid substrate, and its first electrode pads are electrically connected to the second electrode pads arranged on its reverse side. The semiconductor pellet is mounted on the pellet mounting area of the main surface of the base substrate, with its main surface downward, and its bonding pads are connected electrically with the second electrode pads of the base substrate through bonding wires passing through slits formed in the base substrate.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: September 21, 2010
    Assignee: Renesas Electronics Corp.
    Inventors: Atsushi Nakamura, Kunihiko Nishi
  • Patent number: RE42972
    Abstract: A semiconductor device comprising a semiconductor pellet mounted on a pellet mounting area of the main surface of a base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to bonding pads arranged on the main surface of the semiconductor pellet. The base substrate is formed of a rigid substrate, and its first electrode pads are electrically connected to the second electrode pads arranged on its reverse side. The semiconductor pellet is mounted on the pellet mounting area of the main surface of the base substrate, with its main surface downward, and its bonding pads are connected electrically with the second electrode pads of the base substrate through bonding wires passing through slits formed in the base substrate.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: November 29, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Atsushi Nakamura, Kunihiko Nishi
  • Patent number: RE43444
    Abstract: A semiconductor device comprising a semiconductor pellet mounted on a pellet mounting area of the main surface of a base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to bonding pads arranged on the main surface of the semiconductor pellet. The base substrate is formed of a rigid substrate, and its first electrode pads are electrically connected to the second electrode pads arranged on its reverse side. The semiconductor pellet is mounted on the pellet mounting area of the main surface of the base substrate, with its main surface downward, and its bonding pads are connected electrically with the second electrode pads of the base substrate through bonding wires passing through slits formed in the base substrate.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: June 5, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Atsushi Nakamura, Kunihiko Nishi
  • Patent number: RE44148
    Abstract: A semiconductor device comprising a semiconductor pellet mounted on a pellet mounting area of the main surface of a base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to bonding pads arranged on the main surface of the semiconductor pellet. The base substrate is formed of a rigid substrate, and its first electrode pads are electrically connected to the second electrode pads arranged on its reverse side. The semiconductor pellet is mounted on the pellet mounting area of the main surface of the base substrate, with its main surface downward, and its bonding pads are connected electrically with the second electrode pads of the base substrate through bonding wires passing through slits formed in the base substrate.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: April 16, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Atsushi Nakamura, Kunihiko Nishi