Patents by Inventor Kunihiko Nishi
Kunihiko Nishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090072414Abstract: A bonding method (three-dimensional mounting) of semiconductor substrates is provided to sequentially bond a principal surface of a silicon wafer on which coupling bumps are formed, and a principal surface of the other silicon wafer on which pads are formed, by an adhesive applied to at least one of the principal surfaces. However, there is a problem of poor electrical coupling due to displacement of the bumps and the pads when bonded together. The present invention solves such a problem by conducting temporary positioning of the silicon wafers, adjusting the positions of the coupling bumps and pads while confirming the positions by a method such as x-ray capable of passing through the silicon wafers, and bonding the bumps and the pads together while hardening an interlayer adhesive provided between the principal surfaces of the silicon wafers by thermocompression.Type: ApplicationFiled: August 7, 2008Publication date: March 19, 2009Inventors: Hiroyuki TENMEI, Kunihiko NISHI, Yasuhiro NAKA, Nae HISANO, Hiroaki IKEDA, Masakazu ISHINO
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Patent number: 7420284Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.Type: GrantFiled: July 25, 2006Date of Patent: September 2, 2008Assignee: Renesas Technology Corp.Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masnori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
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Publication number: 20080164575Abstract: A method for manufacturing a semiconductor device includes the steps of forming first and second semiconductor wafers each including an array of chips and elongate electrodes, forming a groove on scribe lines separating the chips from one another; coating a surface of one of the semiconductor wafers with adhesive; bonding together the semiconductor wafers while allowing the groove to receive therein excessive adhesive; and heating the wafers to connect the elongate electrodes of both the semiconductor wafers.Type: ApplicationFiled: December 14, 2007Publication date: July 10, 2008Applicant: ELPIDA MEMORY, INC.Inventors: Hiroaki Ikeda, Masakazu Ishino, Hiroyuki Tenmei, Naoya Kanda, Yasuhiro Naka, Kunihiko Nishi
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Publication number: 20080136024Abstract: In a semiconductor device provided by preventing connection failure caused by misalignment of a semiconductor element having fine and narrow-pitched bumps, a guide for preventing the misalignment is formed by an insulating resin layer around a connection electrode. The insulating resin layer has a thickness defined in relation to an angle ? formed by a side wall of the opening and alignment accuracy ? for the bump. Specifically, the thickness of the insulating resin layer may be ? tan ? or more.Type: ApplicationFiled: November 29, 2007Publication date: June 12, 2008Applicant: ELPIDA MEMORY, INC.Inventors: Yasuhiro NAKA, Hiroyuki Tenmei, Kunihiko NISHI, Hiroaki IKEDA, Masakazu ISHINO
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Publication number: 20070298545Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.Type: ApplicationFiled: July 20, 2007Publication date: December 27, 2007Inventors: Yoshinori MIYAKI, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
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Patent number: 7247576Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.Type: GrantFiled: October 28, 2005Date of Patent: July 24, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
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Publication number: 20060261494Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.Type: ApplicationFiled: July 25, 2006Publication date: November 23, 2006Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
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Patent number: 7091620Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.Type: GrantFiled: April 28, 2005Date of Patent: August 15, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Akita Electronics Systems, Co., Ltd.Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masnori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Hiroshi Koyama, Akira Nagai, Masahiko Ogino
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Publication number: 20060049499Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.Type: ApplicationFiled: October 28, 2005Publication date: March 9, 2006Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
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Patent number: 6989334Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.Type: GrantFiled: May 15, 2003Date of Patent: January 24, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
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Patent number: 6981585Abstract: In surface packaging of thin resin packages such as resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging. To solve this problem, the devices are packaged moisture-tight at an assembly step of the resin molded devices where the resin is still dry, and are taken out from the bags immediately before the execution of surface packaging.Type: GrantFiled: July 30, 2002Date of Patent: January 3, 2006Assignee: Renesas Technology Corp.Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
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Publication number: 20050258524Abstract: A manufacturing method of a semiconductor device including preparing a lead frame having a die pad, leads arranged around the die pad and a silver plating layer formed over a first portion of each of the leads, mounting a semiconductor chip over a main surface of the die pad with a rear surface of the chip fixed to the main surface of the die pad, electrically connecting electrodes of the chip with the leads through wires, forming a molding resin sealing the die pad, the first portion, the semiconductor chip, and the wires, and forming a lead-free solder plating layer over a second portion of each of the leads exposed from the molding resin. An area of the die pad is smaller than an area of the chip, and a part of the molding resin contacts with the rear surface of the chip exposed from the die pad.Type: ApplicationFiled: June 17, 2005Publication date: November 24, 2005Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Kunihiko Nishi
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Patent number: 6960823Abstract: To improve a reflow characteristic and realize leadlessness. A semiconductor device comprises a cross die pad which supports a semiconductor chip and in which an area of the region joined to the semiconductor chip is smaller than that of the outer size thereof being smaller than the rear surface of the semiconductor chip; wires connected to pads of the semiconductor chip; a plurality of inner leads which are arranged around the semiconductor chip and in which a silver plating layer is formed at a wire bonding area; molding resin for resin sealing the semiconductor chip; a plurality of outer leads exposed from the molding resin and in which a lead-free metallic layer is formed on a contact surface, wherein the flat surface size of the molding resin is formed to be equal to or less than 28 mm×28 mm and the thickness thereof is formed to be 1.4 mm or less, and thereby it is possible to improve a reflow characteristic and realize leadlessness.Type: GrantFiled: April 4, 2002Date of Patent: November 1, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Kunihiko Nishi
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Publication number: 20050212142Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.Type: ApplicationFiled: April 28, 2005Publication date: September 29, 2005Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masnori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Hiroshi Koyama, Akira Nagai, Masahiko Ogino
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Publication number: 20050200019Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.Type: ApplicationFiled: April 28, 2005Publication date: September 15, 2005Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masnori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Hiroshi Koyama, Akira Nagai, Masahiko Ogino
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Patent number: 6943456Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.Type: GrantFiled: February 13, 2004Date of Patent: September 13, 2005Assignees: Hitachi Ulsi Systems Co., Ltd., Hitachi, Ltd.Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
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Publication number: 20050196903Abstract: A manufacturing method of a semiconductor device including preparing a lead frame having a die pad, leads arranged around the die pad and a silver plating layer formed over a first portion of each of the leads, mounting a semiconductor chip over a main surface of the die pad with a rear surface of the chip fixed to the main surface of the die pad, electrically connecting electrodes of the chip with the leads through wires, forming a molding resin sealing the die pad, the first portion, the semiconductor chip, and the wires, and forming a lead-free solder plating layer over a second portion of each of the leads exposed from the molding resin. An area of the die pad is smaller than an area of the chip, and a part of the molding resin contacts with the rear surface of the chip exposed from the die pad.Type: ApplicationFiled: April 7, 2005Publication date: September 8, 2005Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Kunihiko Nishi
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Publication number: 20050167808Abstract: A semiconductor device comprising a semiconductor chip having an electrode on a circuit formation surface thereof, a flexible film having a lead attached thereto and electrically connected to said electrode of said semiconductor chip through a bump, a resin for covering said circuit formation surface of said semiconductor chip and a resin film for covering a back surface facing said circuit formation surface of said semiconductor chip.Type: ApplicationFiled: March 30, 2005Publication date: August 4, 2005Inventors: Masako Sasaki, Kazunari Suzuki, Seiichi Ichihara, Tomoaki Kudaishi, Hisao Nakamura, Kunihiko Nishi, Hideki Tanaka, Yutaka Nakajima
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Patent number: 6919622Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: February 10, 2004Date of Patent: July 19, 2005Assignee: Renesas Technology Corp.Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
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Patent number: 6867123Abstract: A semiconductor wafer which has finished formation of a relocating wiring layer thereon is stored and after determination of a design, solder bumps are formed over bump lands (one end of the relocating wiring layer) in accordance with a pattern which differs with a design, whereby a function or characteristic depending on the design is selected. The semiconductor wafer is then cut into a plurality of semiconductor chips, whereby a wafer level CSP is available.Type: GrantFiled: November 30, 2001Date of Patent: March 15, 2005Assignee: Renesas Technology Corp.Inventors: Mitsuaki Katagiri, Yuji Shirai, Kunihiko Nishi, Takehiro Ohnishi