Patents by Inventor Kunihiro Harayama

Kunihiro Harayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190392773
    Abstract: A display device includes a display panel, a gate driver that supplies scan signals to a first to nth scan lines, a data driver that supplies gradation voltage signals corresponding to a video data signal to a plurality of data lines, and a display controller that supplies the video data signal to the data driver. The display controller supplies a first to nth pieces of display data to the data driver in units of display data pairs each including a kth piece of display data and an (n+1?k)th piece of display data. The gate driver supplies the scan signals to the plurality of scan lines. Each of the scan signals has different pulse widths depending on distance from the data driver to the respective first to nth scan lines. The data driver supplies the gradation voltage signals to the plurality of data lines on the basis of supply of the display data pairs from the display controller.
    Type: Application
    Filed: June 25, 2019
    Publication date: December 26, 2019
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Koji HIGUCHI, Kunihiro HARAYAMA
  • Patent number: 9537505
    Abstract: A data processing apparatus includes an inputting portion; a first retrieving portion; a second retrieving portion; a clock determining portion; a first serial parallel converting portion; a second serial parallel converting portion; and a combining portion. The inputting portion receives a serial data including a clock bit. The first retrieving portion obtains a first retrieved data. The second retrieving portion obtains a second retrieved data. The clock determining portion determines whether the clock bit is included in the first retrieved data or the second retrieved data. The first serial parallel converting portion performs parallel conversion to obtain a first parallel data. The second serial parallel converting portion performs parallel conversion to obtain a second parallel data. The combining portion combines the first parallel data and the second parallel data to output a parallel data.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: January 3, 2017
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Hiroyoshi Ichikura, Kunihiro Harayama, Hideaki Hasegawa
  • Publication number: 20160173107
    Abstract: A clock data recovery circuit is configured to receive an input data signal formed of a series of input data pieces synchronized with a reference clock signal, and to generate a regenerated clock signal. The clock data recovery circuit includes a regenerated clock generating circuit; a latch circuit; a comparison circuit; a logical sum signal generating circuit; and a charge pump.
    Type: Application
    Filed: December 9, 2015
    Publication date: June 16, 2016
    Inventor: Kunihiro HARAYAMA
  • Patent number: 9356610
    Abstract: A clock data recovery circuit is configured to receive an input data signal formed of a series of input data pieces synchronized with a reference clock signal, and to generate a regenerated clock signal. The clock data recovery circuit includes a regenerated clock generating circuit; a latch circuit; a comparison circuit; a logical sum signal generating circuit; and a charge pump.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: May 31, 2016
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Kunihiro Harayama
  • Publication number: 20160072522
    Abstract: A data processing apparatus includes an inputting portion; a first retrieving portion; a second retrieving portion; a clock determining portion; a first serial parallel converting portion; a second serial parallel converting portion; and a combining portion. The inputting portion receives a serial data including a clock bit. The first retrieving portion obtains a first retrieved data. The second retrieving portion obtains a second retrieved data. The clock determining portion determines whether the clock bit is included in the first retrieved data or the second retrieved data. The first serial parallel converting portion performs parallel conversion to obtain a first parallel data. The second serial parallel converting portion performs parallel conversion to obtain a second parallel data. The combining portion combines the first parallel data and the second parallel data to output a parallel data.
    Type: Application
    Filed: September 8, 2015
    Publication date: March 10, 2016
    Inventors: Hiroyoshi ICHIKURA, Kunihiro HARAYAMA, Hideaki HASEGAWA
  • Patent number: 8901976
    Abstract: A synchronizing circuit that is capable of generating a reproduced clock signal synchronized with a reference clock signal without causing a false lock and a clock data recovery circuit including the same are provided. To generate a clock signal synchronized with a reference clock signal associated with a data transition point that appears every predetermined period in an input data signal, the following false-lock avoidance processing is performed. That is, precharging of a first line is started when a phase control voltage applied to the first line by a charge pump falls below a lower-limit reference voltage, and the precharging of the first line is continued until the phase control voltage exceeds an upper-limit reference voltage.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: December 2, 2014
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Akira Nakayama, Kunihiro Harayama
  • Publication number: 20140118040
    Abstract: A synchronizing circuit that is capable of generating a reproduced clock signal synchronized with a reference clock signal without causing a false lock and a clock data recovery circuit including the same are provided. To generate a clock signal synchronized with a reference clock signal associated with a data transition point that appears every predetermined period in an input data signal, the following false-lock avoidance processing is performed. That is, precharging of a first line is started when a phase control voltage applied to the first line by a charge pump falls below a lower-limit reference voltage, and the precharging of the first line is continued until the phase control voltage exceeds an upper-limit reference voltage.
    Type: Application
    Filed: October 28, 2013
    Publication date: May 1, 2014
    Applicant: Lapis Semiconductor Co., Ltd.
    Inventors: Akira NAKAYAMA, Kunihiro HARAYAMA
  • Patent number: 8384643
    Abstract: A drive circuit for driving a display panel includes a first operation amplifier for operating using a first power source voltage and a second power source voltage; a second operation amplifier for operating using a third power source voltage and a fourth power source voltage; a control unit for supplying a first control voltage and a second control voltage; and a switch circuit for switching the first operation amplifier and the second operation amplifier. The switch circuit includes an n-channel type field effect transistor. The control unit applies the first control voltage to the n-channel type field effect transistor, so that the n-channel type field effect transistor transits from a non-conductive state to a conductive state.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: February 26, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Hideaki Hasegawa, Kunihiro Harayama, Koji Higuchi, Atsushi Hirama
  • Publication number: 20110157120
    Abstract: A drive circuit for driving a display panel includes a first operation amplifier for operating using a first power source voltage and a second power source voltage; a second operation amplifier for operating using a third power source voltage and a fourth power source voltage; a control unit for supplying a first control voltage and a second control voltage; and a switch circuit for switching the first operation amplifier and the second operation amplifier. The switch circuit includes an n-channel type field effect transistor. The control unit applies the first control voltage to the n-channel type field effect transistor, so that the n-channel type field effect transistor transits from a non-conductive state to a conductive state.
    Type: Application
    Filed: December 15, 2010
    Publication date: June 30, 2011
    Inventors: Hideaki HASEGAWA, Kunihiro Harayama, Koji Higuchi, Atsushi Hirama