Abstract: A bit line resetting signal is supplied to the gate of an nMOS transistor (or a precharge circuit) which connects a bit line with a precharge voltage line. The high-level voltage of the bit line resetting signal is retained at a first voltage during the precharge operation after a refresh operation, and is retained at a second voltage higher than the first voltage during the precharge operation after an access operation. In the precharge operation after the refresh operation, therefore, the second voltage is not used so that the current consumption of the generating circuit of the second voltage is reduced. Thus, it is possible to reduce the current consumption (or the standby current) during the standby period for which the internal refresh requests continuously occur.

Abstract: A semiconductor memory device with low power consumption in driving control signals of shift registers. The device contains a plurality of memory cell arrays each composed of a predetermined number of rows of memory cells. One set of shift registers are coupled to each cell array, and the nth set of shift registers successively activate word line selection signals according to a given control signal, so that the corresponding word lines of the nth cell array will be refreshed. Also coupled to each cell array is a shift register controller. The nth shift register controller provides a control signal to the nth set of shift registers when the nth cell array is being refreshed. When the refresh of that cell array is finished, the nth shift register controller forwards the control signal to the (n+1)th set of shift registers, thus initiating refresh operation for the (n+1)th cell array.

Abstract: A semiconductor memory device with low power consumption in driving control signals of shift registers. The device contains a plurality of memory cell arrays each composed of a predetermined number of rows of memory cells. One set of shift registers are coupled to each cell array, and the nth set of shift registers successively activate word line selection signals according to a given control signal, so that the corresponding word lines of the nth cell array will be refreshed. Also coupled to each cell array is a shift register controller. The nth shift register controller provides a control signal to the nth set of shift registers when the nth cell array is being refreshed. When the refresh of that cell array is finished, the nth shift register controller forwards the control signal to the (n+1)th set of shift registers, thus initiating refresh operation for the (n+1)th cell array.

Abstract: Out of memory blocks arranged in one direction, the memory blocks arranged at both ends are included in a partial area. Since part of control circuits operating the memory blocks arranged at the both ends are not shared by the other memory blocks, switching circuits connecting these control circuits to the memory blocks are constantly settable to an ON state. Since ON/OFF control of the switching circuits is not necessary, power consumption required for accessing the memory blocks arranged at the both ends is smaller than that required for accessing the other memory blocks. Therefore, including the memory blocks arranged at the both ends in a partial area makes it possible to reduce power consumption during a partial refresh mode (standby current).

Abstract: In a semiconductor memory device having an error-correction function: one or both of a portion of a set of data bits and a set of parity bits based on the set of data bits are held, where the set of data bits and the set of parity bits constitute a code for error correction and are written in memory cells in the leading write cycle in a burst write operation. The set of parity bits written in memory cells in the leading write cycle is updated in the final write cycle on the basis of the portion of the set of data bits and/or the set of parity bits, and another set of data bits required to be written in the final write cycle in the memory cells at the address at which the above portion is written in the leading write cycle.

Abstract: A semiconductor device includes signal lines over which signals are transferred, and a drive circuit driving the signal lines in operating modes. The operating modes include a dynamic operation mode in which the signal lines are precharged, and a static operation mode in which the signal lines are not precharged.

Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.

Abstract: Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal (in the case shown in FIG. 1, an external upper limit fetch signal) is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.

Abstract: A normal write data selection circuit operates in the normal operation mode, and thus outputs data received through external data terminals to any one of regular cell arrays selected according to an address. A test write control circuit operates in the test mode, and thus writes test data into a regular memory cell at a location corresponding to a location of a parity memory cell into which test parity data are written in each of regular cell arrays. Therefore, since a common test pattern can be used to test both the regular memory cell and the parity memory cell, test cost can be curtailed.

Abstract: Disposed on both sides of a parity cell array are a first regular cell array and a sub parity generation circuit therefor, and a second regular cell array and a sub parity generation circuit therefor. The sub parity generation circuit generates sub parity data according to read data that are simultaneously read from the first and second regular cell arrays. A main parity generation circuit generates according to sub parity data parity data in common to the regular cell arrays, is not disposed in a distributed manner but disposed corresponding to the parity cell array. Thus, the layout design, layout verification, and so forth of a semiconductor memory can be prevented from being complexed. As a result, the parity generation circuit can be optimally laid out, decreasing the development time and defect analysis time for the semiconductor memory can be decreased.

Abstract: A semiconductor device includes signal lines over which signals are transferred, and a drive circuit driving the signal lines in operating modes. The operating modes include a dynamic operation mode in which the signal lines are precharged, and a static operation mode in which the signal lines are not precharged.

Abstract: Regular data inputted/outputted to/from external terminals is read/written to/from a regular cell array, and parity data is read/written from/to a parity cell array. Since the parity data is generated by a parity generation circuit, it is difficult to write a desired pattern to the parity cell array. The regular data and the parity data are exchanged with each other by a switch circuit, so that the regular data can be written to the parity cell array and the parity data can be written to the regular cell array. This enables the write of desired data to the parity cell array. A test of the parity data can be easily conducted. In particular, a leakage test or the like between memory cells can be easily conducted.

Abstract: A memory system that can enhance yield without increasing the chip size and without degrading the access time. A single-bit error determination circuit references parity bits required to configure a code capable of correcting a single-bit error, and determines a single-bit error to be corrected; and a double-bit error detection circuit references one redundant bit added to the parity bits, detects a double-bit error, and enables or disables the double-bit error detection in accordance with a selection signal.

Abstract: A semiconductor device which is driven by a first potential, a second potential lower than the first potential, and a third potential lower than the second potential includes a first Pch transistor and a first Nch transistor connected in series between the first potential and the third potential, a second Pch transistor having a drain node thereof connected to a gate node of the first Nch transistor, and a second Nch transistor having a source node thereof connected to a source node of the second Pch transistor, wherein the drain node and gate node of the second Nch transistor are fixed to the second potential and the first potential, respectively.

Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.

Abstract: A semiconductor memory device includes a plurality of word decoders arranged in a plurality of columns, a plurality of word line selecting shift registers corresponding to the respective word decoders to indicate a word line subjected to refresh operation, and a shift control signal generating circuit operable to supply a shift control signal indicative of timing of shift operations to the plurality of word line selecting shift registers, wherein the said shift control signal generating circuit is configured to supply the shift control signal only to a column currently subjected to refresh operation among the plurality of columns.

Abstract: A semiconductor memory device includes a plurality of first fuse latch circuits configured to provide redundancy to first addresses, a plurality of second fuse latch circuits configured to provide redundancy to second addresses, and a nullifying circuit configured to make the plurality of second fuse latch circuits ineffective, wherein first fuse positions corresponding to the plurality of first fuse latch circuits intervene between second fuse positions corresponding to the plurality of second fuse latch circuits.

Abstract: A memory device includes plural banks (BNKA, BNKB, BNKC, and BNKD), and each of the banks includes a plural memory cells storing data and plural bit lines reading data from the plural memory cells. Bit line lengths of all of the plural banks are equal.

Abstract: A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit.

Abstract: A nonvolatile semiconductor memory device comprises a memory cell array in which memory cells each holding memory cell information are arrayed, reference cells which supply different reference currents respectively, and a read-out circuit. When reading the memory cell information from a selected one of the memory cells, the read-out circuit is brought into conduction to a first global bit line which is connected to a bit line of the selected memory cell, and brought into conduction to one of a plurality of second global bit lines respectively which are provided near the first global bit line and connected to bit lines of non-selected memory cells but not connected to the bit line of the selected memory cell, so that the memory cell information is determined by comparing a read-out current from the selected memory cell with each of the reference currents from the reference cells.