Abstract: A semiconductor memory device includes a plurality of word decoders arranged in a plurality of columns, a plurality of word line selecting shift registers corresponding to the respective word decoders to indicate a word line subjected to refresh operation, and a shift control signal generating circuit operable to supply a shift control signal indicative of timing of shift operations to the plurality of word line selecting shift registers, wherein the said shift control signal generating circuit is configured to supply the shift control signal only to a column currently subjected to refresh operation among the plurality of columns.

Abstract: A semiconductor device which is driven by a first potential, a second potential lower than the first potential, and a third potential lower than the second potential includes a first Pch transistor and a first Nch transistor connected in series between the first potential and the third potential, a second Pch transistor having a drain node thereof connected to a gate node of the first Nch transistor, and a second Nch transistor having a source node thereof connected to a source node of the second Pch transistor, wherein the drain node and gate node of the second Nch transistor are fixed to the second potential and the first potential, respectively.

Abstract: A memory device has a data line (DATA-BUS) for connection to a memory cell, a reference line (Reference-BUS) for reference, a precharge circuit (101), a load circuit (102), and an amplifier circuit (103). The precharge circuit is connected to the data line and the reference line and configured to precharge the data line and the reference line. The load circuit is connected to the data line and the reference line and configured to apply a first constant current to the data line and apply a second constant current which is smaller than the first constant current to the reference line. The amplification circuit is connected to the data line and the reference line and configured to amplify a differential voltage between the data line and the reference line.

Abstract: A semiconductor memory device with low power consumption in driving control signals of shift registers. The device contains a plurality of memory cell arrays each composed of a predetermined number of rows of memory cells. One set of shift registers are coupled to each cell array, and the nth set of shift registers successively activate word line selection signals according to a given control signal, so that the corresponding word lines of the nth cell array will be refreshed. Also coupled to each cell array is a shift register controller. The nth shift register controller provides a control signal to the nth set of shift registers when the nth cell array is being refreshed. When the refresh of that cell array is finished, the nth shift register controller forwards the control signal to the (n+1)th set of shift registers, thus initiating refresh operation for the (n+1)th cell array.

Abstract: A semiconductor integrated circuit device comprises a plurality of MIS transistors, and an integrated circuit unit including logic gate circuits configured by a combination of the plurality of MIS transistors. Each of the MIS transistors has a gate including a circuit element represented by an equivalent circuit in which a capacitance and resistance are parallel-connected.

Abstract: A semiconductor device includes a first latch which receives an input signal, and holds the input signal during a half cycle period of a first clock signal, a delay element coupled to an output of the first latch, a second latch which is coupled to an output of the delay element, and holds a signal output from the delay element during a half cycle period of a second clock signal, and a circuit which adjusts at least one of the first clock signal and the second clock signal such that the signal latched by the first latch during the half cycle period of the first clock signal is latched via the delay element by the second latch during the half cycle period of the second clock signal that follows the half cycle period of the first clock signal.

Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.

Abstract: The present invention is a memory circuit which selects N number of segments out of M number of segments (N<M) during normal reading, wherein all the M number of segments are activated during a read test in order to drive a common data bus for testing by a plurality of sense buffers in the M number of segments. For this, test signals are supplied to a column decoder, and segment select signals, for activating the M number of segments, are generated in response to the test signal. In this way, a plurality of segments in a memory bank in a select status can be simultaneously selected to execute a read test, and the efficiency of a compression read test can be improved.

Abstract: A semiconductor device includes a word line drive circuit resetting the word line by driving the word line connected to a memory cell and switching a reset level of the word line drive circuit at the time of the reset operation of the word line. Further, a semiconductor device includes a memory cell array formed by arranging a plurality of memory cells and a reset level switch circuit for selecting a first potential or a second potential and supplying the first potential or the second potential to the word line drive circuit.

Abstract: A semiconductor integrated circuit, comprising a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit by a combination of a plurality of transistors, is disclosed. Among a plurality of the transistors of the circuit unit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed. Preferably, the semiconductor integrated circuit is configured to reduce the sub-threshold current flowing between the source and the drain of at least one transistor adapted to turn off during the standby period of the circuit unit by changing the source potential at a timing based on the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and the source of the transistor. A method of switching the source potential of at least one transistor in the semiconductor integrated circuit having the configuration described above is also disclosed.

Abstract: A semiconductor memory comprises a sense amplifier for amplifying a signal quantity of data transmitted to the bit line. The sense amplifier includes a transistor for electrically connecting, to the bit line, an input/output node of data which is read from/written in the memory cell, and for transmitting the data. The transistor is operated not only during data amplification of the sense amplifier but also in advance prior to the data amplification. Along with the operation of the transistor, a voltage of the bit line is changed by a coupling capacitance of the transistor and the bit line. Namely, the voltage of the bit line is shifted before the data held in the memory cell is transmitted to the bit line. Thus, it is possible to improve read margins of read data without forming a dedicated capacitance. As a result, the size of a chip can be decreased.

Abstract: A semiconductor device includes a first latch which receives an input signal, and holds the input signal during a half cycle period of a first clock signal, a delay element coupled to an output of the first latch, a second latch which is coupled to an output of the delay element, and holds a signal output from the delay element during a half cycle period of a second clock signal, and a circuit which adjusts at least one of the first clock signal and the second clock signal such that the signal latched by the first latch during the half cycle period of the first clock signal is latched via the delay element by the second latch during the half cycle period of the second clock signal that follows the half cycle period of the first clock signal.

Abstract: A semiconductor device characterized by comprising a first insulating film formed on the semiconductor substrate, a first wiring or mark formed on the first insulating film, an electrically isolated pattern formed under the first insulating film and below the first wiring or mark, a hole formed in the first insulating film to connect the first wiring or mark and the electrically isolated pattern, and a second insulating film for covering the first wiring or mark.

Abstract: Read amplifiers are arranged adjacent to each other near the center of an amplifier string, thereby shortening the distances of read data paths from sense amplifiers to the read amplifiers. This can suppress the delay of a read operation caused by the wiring resistance of a data bus line, to realize high-speed read and write operations by reducing the wiring load on data paths in data read and write.

Abstract: A semiconductor integrated circuit, comprising a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit by a combination of a plurality of transistors, is disclosed. Among a plurality of the transistors of the circuit unit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed. Preferably, the semiconductor integrated circuit is configured to reduce the sub-threshold current flowing between the source and the drain of at least one transistor adapted to turn off during the standby period of the circuit unit by changing the source potential at a timing based on the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and the source of the transistor. A method of switching the source potential of at least one transistor in the semiconductor integrated circuit having the configuration described above is also disclosed.

Abstract: A semiconductor integrated circuit device comprises a plurality of MIS transistors, and an integrated circuit unit including logic gate circuits configured by a combination of the plurality of MIS transistors. Each of the MIS transistors has a gate including a circuit element represented by an equivalent circuit in which a capacitance and resistance are parallel-connected.

Abstract: A semiconductor memory device has a segment type word line structure and comprises a plurality of main word lines and a plurality of sub word lines which are arranged at different levels. The semiconductor memory device is provided with a memory cell array divided into a plurality of cell array blocks. A plurality of sub row decoder areas, each for selecting one of the sub word lines, are defined between the cell array blocks. A plurality of first metal wiring lines formed by use of the same wiring layer as the main word lines are provided. The first metal wiring lines pass across the sub row decoder areas and the cell array blocks.

Abstract: A semiconductor memory comprises a sense amplifier for amplifying a signal quantity of data transmitted to the bit line. The sense amplifier includes a transistor for electrically connecting, to the bit line, an input/output node of data which is read from/written in the memory cell, and for transmitting the data. The transistor is operated not only during data amplification of the sense amplifier but also in advance prior to the data amplification. Along with the operation of the transistor, a voltage of the bit line is changed by a coupling capacitance of the transistor and the bit line. Namely, the voltage of the bit line is shifted before the data held in the memory cell is transmitted to the bit line. Thus, it is possible to improve read margins of read data without forming a dedicated capacitance. As a result, the size of a chip can be decreased.

Abstract: A semiconductor device includes signal lines over which signals are transferred, and a drive circuit driving the signal lines in operating modes. The operating modes include a dynamic operation mode in which the signal lines are precharged, and a static operation mode in which the signal lines are not precharged.

Abstract: Read amplifiers are arranged adjacent to each other near the center of an amplifier string, thereby shortening the distances of read data paths from sense amplifiers to the read amplifiers. This can suppress the delay of a read operation caused by the wiring resistance of a data bus line, to realize high-speed read and write operations by reducing the wiring load on data paths in data read and write.