Abstract: In-vehicle detection system includes nonvolatile memory, a controller (SoC) that reads and writes data from and in nonvolatile memory, and detector that outputs detection information to SoC. SoC changes a control signal of nonvolatile memory in accordance with the output of detector.

Abstract: In-vehicle detection system includes nonvolatile memory, a controller (SoC) that reads and writes data from and in nonvolatile memory, and detector that outputs detection information to SoC. SoC changes a control signal of nonvolatile memory in accordance with the output of detector.

Abstract: A semiconductor memory device includes a memory cell array, a plurality of reference cell arrays, a plurality of word lines, a plurality of bit lines, a plurality of reference word lines, a plurality of reference bit lines each being provided for an associated one of the reference cell arrays, and equalizing transistors each of which is provided between the plurality of reference bit lines and receives an associated one of independent control signals, and a potential of one of the plurality of reference bit lines and a plurality of one of the plurality of bit lines are input to a sense amplifier.

Abstract: There are provided a first nonvolatile memory array including a plurality of nonvolatile memory elements which require an erase operation before a write operation, and a second nonvolatile memory array including a plurality of overwritable nonvolatile memory elements. A request to rewrite data is received by a control circuit. The control circuit writes data to be rewritten to the second nonvolatile memory array when the capacity of the data to be rewritten is not more than that of the second nonvolatile memory array.

Abstract: There are provided a first nonvolatile memory array including a plurality of nonvolatile memory elements which require an erase operation before a write operation, and a second nonvolatile memory array including a plurality of overwritable nonvolatile memory elements. A request to rewrite data is received by a control circuit. The control circuit writes data to be rewritten to the second nonvolatile memory array when the capacity of the data to be rewritten is not more than that of the second nonvolatile memory array.

Abstract: A ferro-electric memory device suppresses deterioration of retention characteristics at the time when an ambient temperature has decreased, without requiring a much longer cycle time. The ferro-electric memory device includes a first ferro-electric capacitor for use in a first normal cell and a second ferro-electric capacitor for use in a second normal cell. The ferro-electric memory device also includes: a temperature detection circuit which detects an ambient temperature of the first and second normal cells; and a normal cell power supply switching circuit which switches a voltage to be applied to the first and second ferro-electric capacitors depending on the detected temperature.

Abstract: In order to omit a reset transistor between a storage node and a cell plate line of a memory cell, a cell plate line is fixed to a potential substantially equal to a ground potential and a bit line is driven with positive and negative voltages.

Abstract: A ferroelectric memory of the present invention comprises: a plurality of normal cells, each of which includes a first ferroelectric capacitor for holding data and a first transistor connected to a first electrode of the first ferroelectric capacitor; a first bit line connected to the first transistor; a first bit line precharge circuit which is a switch circuit provided between the first bit line and a ground; and a word line connected to a gate of the first transistor. The word line is deactivated to disconnect the first ferroelectric capacitor from the first bit line before the first bit line precharge circuit is driven to discharge a potential of the first bit line.

Abstract: Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

Abstract: There is provided a method for controlling a semiconductor memory which includes a memory cell array including a plurality of multivalued memory cells where, in each of the memory cells, a first write operation allows storage of data in a first page address and a second write operation allows storage of data in a second page address, the method comprising an address conversion table processing step and an address scramble step. At the address conversion table processing step, an address conversion table for address conversion is generated by, in each of the plurality of multivalued memory cells, allocating addresses in which writing is to be performed to addresses such that data is written in a second page address after writing of data in a first page address. At the address scramble step, address conversion is performed on an input address according to the address conversion table.

Abstract: In order to omit a reset transistor between a storage node and a cell plate line of a memory cell, a cell plate line is fixed to a potential substantially equal to a ground potential and a bit line is driven with positive and negative voltages.

Abstract: The present invention provides a ferroelectric semiconductor memory device in which the potential of data read out from a normal cell is compared with the reference level of a reference cell so as to determine whether the readout data is the “H” data or the “L” data, wherein since the reference cell is in the relaxed state when reading out data from the normal cell for the first time, the reference cell is reset before reading out data from the normal cell. Then, data is read out from the normal cell, and then the reference cell is reset. In second and subsequent data read operations of reading out data from a normal cell of another address, the reference cell is in the reset state, whereby the reference level is the same between the first data read operation and the second or subsequent data read operation. Thus, the reference level is always kept at a predetermined constant level when data is read out from normal cells.

Abstract: To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.

Abstract: In a ferro-electric memory including reference cells, if one reference cell is associated with a plurality of normal cells, a period in which “L” data is written in the reference cell and a period in which “H” data is written or read out in/from the reference cell are controlled to be shorter than a period in which “L” data is written in each normal cell and a period in which “H” data is written or read out in/from each normal cell, respectively. In this manner, stress applied to the reference cell is reduced and, even if writing or reading is repeatedly performed on the normal cells, the reliability of the reference cell is enhanced and deterioration in characteristics of the reference cell due to repetitive rewriting of data is suppressed.

Abstract: The present invention provides a ferro-electric memory device which suppresses the deterioration of the retention characteristics at the time when an ambient temperature has decreased, without requiring much longer cycle time. The ferro-electric memory device includes a first ferro-electric capacitor intended for use in a first normal cell and a second ferro-electric capacitor intended for use in a second normal cell. The ferro-electric memory device includes: a temperature detection circuit which detects an ambient temperature of the first and second normal cells; and a normal cell power supply switching circuit which switches a voltage to be applied to the first and second ferro-electric capacitors depending on the detected temperature.

Abstract: Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

Abstract: To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.

Abstract: A ferroelectric memory of the present invention comprises: a plurality of normal cells, each of which includes a first ferroelectric capacitor for holding data and a first transistor connected to a first electrode of the first ferroelectric capacitor; a first bit line connected to the first transistor; a first bit line precharge circuit which is a switch circuit provided between the first bit line and a ground; and a word line connected to a gate of the first transistor. The word line is deactivated to disconnect the first ferroelectric capacitor from the first bit line before the first bit line precharge circuit is driven to discharge a potential of the first bit line.

Abstract: In a ferro-electric memory including reference cells, if one reference cell is associated with a plurality of normal cells, a period in which “L” data is written in the reference cell and a period in which “H” data is written or read out in/from the reference cell are controlled to be shorter than a period in which “L” data is written in each normal cell and a period in which “H” data is written or read out in/from each normal cell, respectively. In this manner, stress applied to the reference cell is reduced and, even if writing or reading is repeatedly performed on the normal cells, the reliability of the reference cell is enhanced and deterioration in characteristics of the reference cell due to repetitive rewriting of data is suppressed.

Abstract: Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.