Patents by Inventor Kuo-Cheng Ching

Kuo-Cheng Ching has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10825919
    Abstract: A method of fabricating semiconductor devices is provided. The method includes forming a fin structure on a substrate, in which the fin structure includes a fin stack of alternating first and second semiconductor layers and forming recesses in the fin stack at source and drain regions. The method also includes etching the second semiconductor layers to form recessed second semiconductor layers, and forming third semiconductor layers on sidewalls of the recessed second semiconductor layers. The method further includes epitaxially growing source and drain structures in the recesses, removing the recessed second semiconductor layers to form spaces between the first semiconductor layers, and oxidizing the third semiconductor layers to form inner spacers. In addition, the method includes forming a gate structure to fill the spaces and to surround the first semiconductor layers.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung Lin, Pei-Hsun Wang, Chih-Hao Wang, Kuo-Cheng Ching, Jui-Chien Huang
  • Patent number: 10818658
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure on a substrate; a first gate stack and a second gate stack formed on the fin structure; a dielectric material layer disposed on the first and second gate stacks, wherein the dielectric layer includes a first portion disposed on a sidewall of the first gate stack with a first thickness and a second portion disposed on a sidewall of the second gate stack with a second thickness greater than the first thickness; a first gate spacer disposed on the first portion of the dielectric material layer; and a second gate spacer disposed on the second portion of the dielectric material layer.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Ying-Keung Leung, Chi On Chui
  • Patent number: 10811509
    Abstract: A semiconductor device includes a source/drain feature disposed over a substrate. The source/drain feature includes a first nanowire, a second nanowire disposed over the first nanowire, a cladding layer disposed over the first nanowire and the second nanowire and a spacer layer extending from the first nanowire to the second nanowire. The device also includes a conductive feature disposed directly on the source/drain feature such that the conductive feature physically contacts the cladding layer and the spacer layer.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ching-Fang Huang, Carlos H. Diaz, Chih-Hao Wang, Wen-Hsing Hsieh, Ying-Keung Leung
  • Patent number: 10811317
    Abstract: Methods for manufacturing semiconductor structures are provided. The method includes alternately stacking first epitaxy layers and second epitaxy layers to form a semiconductor stack and forming a first mask structure and a second mask structure over the semiconductor stack. The method further includes forming spacers on sidewalls of the second mask and patterning the semiconductor stack to form a first fin structure covered by the first mask structure and a second fin structure covered by the second mask structure and the spacers. The method further includes removing the first epitaxy layers of the first fin structure to form first nanostructures and removing the first epitaxy layers of the second fin structure to form second nanostructures. In addition, the second nanostructures are wider than the first nanostructures.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20200328219
    Abstract: A method includes providing a substrate having an n-type fin-like field-effect transistor (NFET) region and forming a fin structure in the NFET region. The fin structure includes a first layer having a first semiconductor material, and a second layer under the first layer and having a second semiconductor material different from the first semiconductor material. The method further includes forming a patterned hard mask to fully expose the fin structure in gate regions of the NFET region and partially expose the fin structure in at least one source/drain (S/D) region of the NFET region. The method further includes oxidizing the fin structure not covered by the patterned hard mask, wherein the second layer is oxidized at a faster rate than the first layer. The method further includes forming an S/D feature over the at least one S/D region of the NFET region.
    Type: Application
    Filed: June 26, 2020
    Publication date: October 15, 2020
    Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Chih-Sheng Chang, Zhiqiang Wu
  • Patent number: 10804381
    Abstract: A semiconductor device includes a substrate and a fin feature over the substrate. The fin feature includes a first portion having a first semiconductor material and a second portion having a second semiconductor material over the first portion. The second semiconductor material is different from the first semiconductor material. The semiconductor device further includes an isolation feature over the substrate and over sides of the fin feature; a semiconductor oxide feature including the first semiconductor material and disposed on sidewalls of the first portion; and a gate stack disposed on the fin feature and the isolation feature. The gate stack includes a gate dielectric layer extending into recesses that are into a top portion of the semiconductor oxide feature and below the second portion of the fin feature.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Carlos H. Diaz, Chih-Hao Wang, Zhiqiang Wu
  • Publication number: 20200321453
    Abstract: A fin field effect transistor device structure includes a first fin structure formed over a substrate. The structure also includes a fin top layer formed over a top portion of the first fin structure. The structure also includes a first oxide layer formed across the first fin structure and the fin top layer. The structure also includes a first gate structure formed over the first oxide layer across the first fin structure.
    Type: Application
    Filed: June 24, 2020
    Publication date: October 8, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng CHING, Kuan-Ting PAN, Shi-Ning JU, Chih-Hao WANG
  • Publication number: 20200321459
    Abstract: Methods are disclosed herein for fabricating integrated circuit devices, such as fin-like field-effect transistors (FinFETs), and disclosed are the associated devices. An exemplary method includes forming a first semiconductor material layer over a fin portion of a substrate; forming a second semiconductor material layer over the first semiconductor material layer; and converting a portion of the first semiconductor material layer to a first semiconductor oxide layer. The fin portion of the substrate, the first semiconductor material layer, the first semiconductor oxide layer, and the second semiconductor material layer form a fin. The method further includes forming a gate stack overwrapping the fin.
    Type: Application
    Filed: April 20, 2020
    Publication date: October 8, 2020
    Inventors: Chih-Hao WANG, Gwan-Sin CHANG, Kuo-Cheng CHING, Zhiqiang WU
  • Publication number: 20200321339
    Abstract: The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with source/drain (S/D) features and a high-k/metal gate (HK/MG). A first HK/MG in a first gate region wraps over an upper portion of a first fin structure, the first fin structure including an epitaxial silicon (Si) layer as its upper portion and an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion, and the substrate as its bottom portion. A second HK/MG in a second gate region, wraps over an upper portion of a second fin structure, the second fin structure including an epitaxial SiGe layer as its upper portion, an epitaxial Si layer as it upper middle portion, an epitaxial SiGe layer as its lower middle portion, and the substrate as its bottom portion.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Chih-Sheng Chang, Zhiqiang Wu
  • Publication number: 20200312847
    Abstract: A FinFET device includes a fin, an epitaxial layer disposed at a side surface of the fin, a contact disposed on the epitaxial layer and on the fin. The contact includes an epitaxial contact portion and a metal contact portion disposed on the epitaxial contact portion. The doping concentration of the epitaxial contact portion is higher than a doping concentration of the epitaxial layer.
    Type: Application
    Filed: May 18, 2020
    Publication date: October 1, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng CHING, Ching-Wei TSAI, Kuan-Lun CHENG, Chih-Hao WANG
  • Patent number: 10790280
    Abstract: A semiconductor includes a first transistor and a second transistor. The first transistor includes a first and a second epitaxial layer, formed of a first semiconductor material. The second epitaxial layer is disposed over the first epitaxial layer. The first transistor also includes a first gate dielectric layer surrounds the first and second epitaxial layers and extends from a top surface of the first epitaxial layer to a bottom surface of the second epitaxial layer and a first metal gate layer surrounding the first gate dielectric layer. The second transistor includes a third epitaxial layer formed of the first semiconductor material and a fourth epitaxial layer disposed directly on the third epitaxial layer and formed of a second semiconductor. The second transistor also includes a second gate dielectric layer disposed over the third and fourth epitaxial layers and a second metal gate layer disposed over the second gate dielectric layer.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Chung-Cheng Wu, Ching-Fang Huang, Wen-Hsing Hsieh, Ying-Keung Leung, Cheng-Ting Chung
  • Publication number: 20200295155
    Abstract: Semiconductor structures including active fin structures, dummy fin structures, epitaxy layers, a Ge containing oxide layer and methods of manufacture thereof are described. By implementing the Ge containing oxide layer on the surface of the epitaxy layers formed on the source/drain regions of some of the FinFET devices, a self-aligned epitaxy process is enabled. By implementing dummy fin structures and a self-aligned etch, both the epitaxy layers and metal gate structures from adjacent FinFET devices are isolated in a self-aligned manner.
    Type: Application
    Filed: June 2, 2020
    Publication date: September 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng CHING, Kuan-Lun CHENG, Chih-Hao WANG
  • Patent number: 10777554
    Abstract: An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ting-Hung Hsu
  • Publication number: 20200287047
    Abstract: A device includes a semiconductor substrate, a first fin arranged over the semiconductor substrate, and an isolation structure. The first fin includes an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion. A top surface of the insulator layer is wider than a bottom surface of the upper portion of the first fin. The isolation structure surrounds the bottom portion of the first fin.
    Type: Application
    Filed: May 21, 2020
    Publication date: September 10, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Hao KUO, Jung-Hao CHANG, Chao-Hsien HUANG, Li-Te LIN, Kuo-Cheng CHING
  • Publication number: 20200287018
    Abstract: A semiconductor structure includes a substrate, a fin, a bottom capping structure and a top capping structure. The fin disposed on the substrate, the fin has a lower portion and an upper portion extending upwards from the lower portion. The bottom capping structure covers a sidewall of the lower portion of the fin. The top capping structure covers a sidewall of the upper portion of the fin.
    Type: Application
    Filed: May 22, 2020
    Publication date: September 10, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng CHING, Shi-Ning JU, Chih-Hao WANG, Ying-Keung LEUNG
  • Publication number: 20200279778
    Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Kuan-Ting Pan
  • Patent number: 10763365
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Chih-Ming Lai, Ching-Wei Tsai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kuo-Cheng Ching, Ru-Gun Liu, Wei-Hao Wu, Yi-Hsiung Lin, Chia-Hao Chang, Lei-Chun Chou
  • Patent number: 10763255
    Abstract: A semiconductor device has a first fin, a second fin, an isolation structure between the first fin and the second fin, a dielectric stage in the isolation structure, and a helmet layer over the dielectric stage. A top surface of the helmet layer is higher than a top surface of the isolation structure.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Chih-Hao Wang
  • Publication number: 20200273964
    Abstract: A method of fabricating semiconductor devices is provided. The method includes forming a fin structure on a substrate, in which the fin structure includes a fin stack of alternating first and second semiconductor layers and forming recesses in the fin stack at source and drain regions. The method also includes etching the second semiconductor layers to form recessed second semiconductor layers, and forming third semiconductor layers on sidewalls of the recessed second semiconductor layers. The method further includes epitaxially growing source and drain structures in the recesses, removing the recessed second semiconductor layers to form spaces between the first semiconductor layers, and oxidizing the third semiconductor layers to form inner spacers. In addition, the method includes forming a gate structure to fill the spaces and to surround the first semiconductor layers.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 27, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung LIN, Pei-Hsun WANG, Chih-Hao WANG, Kuo-Cheng CHING, Jui-Chien HUANG
  • Patent number: 10755943
    Abstract: A method includes forming a mandrel structure over a semiconductor substrate. A first spacer and a second spacer are formed alongside the mandrel structure. A mask layer is over a first portion of the first spacer, in which a second portion of the first spacer and the second spacer are exposed from the mask layer. The exposed second spacer is etched, in which etching the exposed second spacer is performed such that a polymer is formed over a top surface of the exposed second portion of the first spacer. The mask layer, the polymer, and the mandrel structure are removed. The semiconductor substrate is patterned using the first spacer.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Hao Chang, Chao-Hsien Huang, Wen-Ting Lan, Shi-Ning Ju, Li-Te Lin, Kuo-Cheng Ching