Patents by Inventor Kuo-Cheng Ching

Kuo-Cheng Ching has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200052132
    Abstract: A semiconductor device includes a substrate; a channel member above the substrate; a gate structure wrapping the channel member; a source/drain (S/D) feature abutting the channel member; and an inner spacer interposing the S/D feature and the gate structure, wherein a first sidewall of the inner spacer facing the gate structure has a curvature surface in a cross-sectional view perpendicular to a top surface of the substrate and along a lengthwise direction of the channel member.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 13, 2020
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Guan-Lin Chen, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20200052084
    Abstract: In accordance with an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first cover layer is formed over the sacrificial gate structure, and a second cover layer is formed over the first cover layer. A source/drain epitaxial layer is formed. After the source/drain epitaxial layer is formed, the second cover layer is removed, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed. Part of the first semiconductor layers is removed in the gap, thereby forming spaces between the second semiconductor layers. The spaces are filled with a first insulating material.
    Type: Application
    Filed: October 16, 2019
    Publication date: February 13, 2020
    Inventors: Kuo-Cheng CHING, Ching-Wei TSAI, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20200043810
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device with fin structures having different top surface crystal orientations and/or different materials. The present disclosure provides a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and with fin structures having different materials. The present disclosure provides a method to fabricate a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and different materials to achieve optimized electron transport and hole transport. The present disclosure also provides a diode structure and a bipolar junction transistor structure that includes SiGe in the fin structures.
    Type: Application
    Filed: May 30, 2019
    Publication date: February 6, 2020
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Publication number: 20200043919
    Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a metal gate strip, gate spacers and a dielectric helmet. The substrate has fins. The metal gate strip is disposed across the fins and has a reversed T-shaped portion between two adjacent fins. The gate spacers are disposed on opposing sidewalls of the metal gate strip. A dielectric helmet is disposed over the metal gate strip.
    Type: Application
    Filed: December 11, 2018
    Publication date: February 6, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Huan-Chieh Su, Mao-Lin Huang, Zhi-Chang Lin
  • Patent number: 10553699
    Abstract: A CMOS semiconductor device includes a substrate comprising an isolation region separating a P-active region and an N-active region. The CMOS semiconductor device further includes a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode includes a P-work function metal and a doped TiN layer between the P-work function metal and substrate. The CMOS semiconductor device further includes an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode includes an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein a portion of the P-metal gate electrode is between a portion of the N-metal gate electrode and the substrate.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming Zhu, Hui-Wen Lin, Harry Hak-Lay Chuang, Bao-Ru Young, Yuan-Sheng Huang, Ryan Chia-jen Chen, Chao-Cheng Chen, Kuo-Cheng Ching, Ting-Hua Hsieh, Carlos H. Diaz
  • Publication number: 20200035558
    Abstract: A method of forming a semiconductor device includes providing a device having a gate stack including a metal gate layer. The device further includes a spacer layer disposed on a sidewall of the gate stack and a source/drain feature adjacent to the gate stack. The method further includes performing a first etch-back process to the metal gate layer to form an etched-back metal gate layer. In some embodiments, the method includes depositing a metal layer over the etched-back metal gate layer. In some cases, a semiconductor layer is formed over both the metal layer and the spacer layer to provide a T-shaped helmet layer over the gate stack and the spacer layer.
    Type: Application
    Filed: May 24, 2019
    Publication date: January 30, 2020
    Inventors: Kuo-Cheng CHING, Lin-Yu HUANG, Huan-Chieh SU, Sheng-Tsung WANG, Zhi-Chang LIN, Jia-Chuan YOU, Chia-Hao CHANG, Tien-Lu LIN, Yu-Ming LIN, Chih-Hao WANG
  • Patent number: 10541319
    Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate. The first and second fin structures have respective first and second vertical dimensions that are about equal to each other. The method further includes modifying the first fin structure such that the first vertical dimension of the first fin structure is smaller than the second vertical dimension of the second fin structure and depositing a dielectric layer on the modified first fin structure and the second fin structure. The method further includes forming a polysilicon structure on the dielectric layer and selectively forming a spacer on a sidewall of the polysilicon structure.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: January 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Shi Ning Ju
  • Publication number: 20200020692
    Abstract: A method for fabricating a semiconductor device includes providing a fin in a first region of a substrate. The fin includes a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A portion of a layer of the second type of epitaxial layers in a channel region of the first fin is removed to form a first gap between a first layer of the first type of epitaxial layers and a second layer of the first type of epitaxial layers. A first portion of a first gate structure is formed within the first gap and extending from a first surface of the first layer of the first type of epitaxial layers to a second surface of the second layer of the first type of epitaxial layers. A first source/drain feature is formed abutting the first portion of the first gate structure.
    Type: Application
    Filed: June 11, 2019
    Publication date: January 16, 2020
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20200020782
    Abstract: FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.
    Type: Application
    Filed: April 18, 2019
    Publication date: January 16, 2020
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10529833
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: January 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Teng-Chun Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20200006156
    Abstract: Various methods are disclosed herein for fabricating non-planar circuit devices having strain-producing features. An exemplary method includes forming a fin structure that includes a first portion that includes a first semiconductor material and a second portion that includes a second semiconductor material that is different than the first semiconductor material. The method further includes forming a masking layer over a source region and a drain region of the fin structure, forming a strain-producing feature over the first portion of the fin structure in a channel region, removing the masking layer and forming an isolation feature over the strain-producing feature, forming an epitaxial feature over the second portion of the fin structure in the source region and the drain region, and performing a gate replacement process to form a gate structure over the second portion of the fin structure in the channel region.
    Type: Application
    Filed: September 9, 2019
    Publication date: January 2, 2020
    Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Zhiqiang Wu
  • Publication number: 20200006577
    Abstract: A method of fabricating a semiconductor device includes forming a fin extruding from a substrate, the fin having a plurality of sacrificial layers and a plurality of channel layers, wherein the sacrificial layers and the channel layers are alternately arranged; removing a portion of the sacrificial layers from a channel region of the fin; depositing a spacer material in areas from which the portion of the sacrificial layers have been removed; selectively removing a portion of the spacer material, thereby exposing the channel layers in the channel region of the fin, wherein other portions of the spacer material remain as a spacer feature; and forming a gate structure engaging the exposed channel layers.
    Type: Application
    Filed: March 19, 2019
    Publication date: January 2, 2020
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Guan-Lin Chen, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10522416
    Abstract: The present disclosure provides a method, which includes forming a first fin structure and a second fin structure over a substrate, which has a first trench positioned between the first and second fin structures. The method also includes forming a first dielectric layer within the first trench, recessing the first dielectric layer to expose a portion of the first fin structure, forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin feature and removing the first capping layer from the first fin structure.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ying-Keung Leung
  • Patent number: 10522407
    Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes forming a plurality of fins extending from a substrate. In various embodiments, each of the plurality of fins includes a portion of a substrate, a portion of a first epitaxial layer on the portion of the substrate, and a portion of a second epitaxial layer on the portion of the first epitaxial layer. The portion of the first epitaxial layer of each of the plurality of fins is oxidized, and a liner layer is formed over each of the plurality of fins. Recessed isolation regions are then formed adjacent to the liner layer. The liner layer may then be etched to expose a residual material portion (e.g., Ge residue) adjacent to a bottom surface of the portion of the second epitaxial layer of each of the plurality of fins, and the residual material portion is removed.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Ying-Keung Leung
  • Patent number: 10516051
    Abstract: The present disclosure provides a fin-like field effect transistor (FinFET) device and a method of fabrication thereof. The method includes forming a fin on a substrate and forming a gate structure wrapping the fin. A pair of spacers is formed adjacent to the gate structure and the gate structure is removed. Afterwards, a pair of oxide layers is deposited adjacent to the pair of spacers. A pair of gate dielectric layers is deposited next to the pair of oxide layers. Finally, a metal gate is formed between the pair of gate dielectric layers.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING
    Inventors: Kuo-Cheng Ching, Kuan-Ting Pan, Ching-Wei Tsai, Ying-Keung Leung, Chih-Hao Wang, Carlos H. Diaz
  • Patent number: 10516049
    Abstract: A method of semiconductor device fabrication is described that includes forming a fin extending from a substrate and having a source/drain region and a channel region. The fin includes a first epitaxial layer having a first composition and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second composition. The second epitaxial layer is removed from the source/drain region of the fin to form a gap. The gap is filled with a dielectric material. Another epitaxial material is formed on at least two surfaces of the first epitaxial layer to form a source/drain feature.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Carlos H. Diaz, Chih-Hao Wang, Wai-Yi Lien, Ying-Keung Leung
  • Patent number: 10510873
    Abstract: A semiconductor device has a substrate, a first dielectric fin, and an isolation structure. The substrate has a first semiconductor fin. The first dielectric fin is disposed over the substrate and in contact with a first sidewall of the first semiconductor fin, in which a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin. The isolation structure is in contact with the first semiconductor fin and the first dielectric fin, in which a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10510874
    Abstract: A semiconductor device is disclosed that includes a plurality of isolation regions. A fin is arranged between the plurality of isolation regions. One of the plurality of isolation regions includes a first atomic layer deposition (ALD) layer, a second ALD layer, a flowable chemical vapor deposition (FCVD) layer, and a third ALD layer. The first ALD layer includes a first trench. The second ALD layer is formed in the first trench of the first ALD layer. The FCVD layer is formed in the first trench of the first ALD layer and on the second ALD layer. The third ALD layer is formed on the FCVD layer.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Kuan-Lun Cheng, Chih-Hao Wang, Keng-Chu Lin, Shi-Ning Ju
  • Publication number: 20190371673
    Abstract: The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.
    Type: Application
    Filed: August 19, 2019
    Publication date: December 5, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Kuan-Lun Cheng
  • Patent number: 10497778
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, an isolation plug, and an isolation structure. The semiconductor fin is over the substrate. The isolation plug is over the substrate and adjacent to an end of the semiconductor fin. The isolation structure is over the substrate and adjacent to sidewalls of the semiconductor fin and the isolation plug. A top surface of the isolation structure is in a position lower than a top surface of the isolation plug.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang