Patents by Inventor Kuo-Chih Lai

Kuo-Chih Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130078800
    Abstract: A method for fabricating metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate having a silicide thereon; performing a first rapid thermal process to drive-in platinum from a surface of the silicide into the silicide; and removing un-reacted platinum in the first rapid thermal process.
    Type: Application
    Filed: September 28, 2011
    Publication date: March 28, 2013
    Inventors: Kuo-Chih Lai, Nien-Ting Ho, Shu Min Huang, Bor-Shyang Liao, Chia Chang Hsu
  • Publication number: 20130023098
    Abstract: A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.
    Type: Application
    Filed: July 18, 2011
    Publication date: January 24, 2013
    Inventors: Po-Cheng Huang, Kuo-Chih Lai, Ching-I Li, Yu-Shu Lin, Ya-Jyuan Hung, Yen-Liang Lu, Yu-Wen Wang, Hsin-Chih Yu
  • Publication number: 20130014779
    Abstract: A cleaning method of a semiconductor manufacturing process is provided. The cleaning method is applied to a semiconductor component including a plurality of material layers formed thereon. An opening is defined in the material layers, and a side wall is exposed from the opening The side wall at least includes a first material layer and a second material layer. At first, a first cleaning process is performed till a lateral etched thickness of the first material layer is equal to a lateral etched thickness of the second material layer. Then, a byproduct formed in the first cleaning process is removed.
    Type: Application
    Filed: July 13, 2011
    Publication date: January 17, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Wei CHEN, Teng-Chun TSAI, Kuo-Chih LAI, Shu-Min HUANG
  • Patent number: 8350246
    Abstract: A structure of a porous low-k layer is described, comprising a bottom portion and a body portion of the same atomic composition, wherein the body portion is located on the bottom portion, and the bottom portion has a density higher than the density of the body portion. An interconnect structure is also described, including the above porous low-k layer, and a conductive layer filling up a damascene opening in the porous low-k layer.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: January 8, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Mei-Ling Chen, Kuo-Chih Lai, Su-Jen Sung, Chien-Chung Huang, Yu-Tsung Lai
  • Patent number: 8344465
    Abstract: In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a NixSi layer at middle height down to a front thereof, or before formation of the NixSi layer, located in a region ranging from a silicon layer at a depth ranging from a half of a predetermined thickness of a NiSi layer down to a depth where is a predetermined front of the NiSi layer. The dopant is allowed to be heated with the NixSi layer together during the second thermal process to form a Si/NiSi2/NiSi interface which may reduce SBH and improve series resistance to obtain a semiconductor device having an excellent performance.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: January 1, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Wei Chen, Nien-Ting Ho, Kuo-Chih Lai, Chien-Chung Huang
  • Publication number: 20120181635
    Abstract: In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a NixSi layer at meddle height down to a front thereof, or before formation of the NixSi layer, located in a region ranging from a silicon layer at a depth ranging from a half of a predetermined thickness of a NiSi layer down to a depth where is a predetermined front of the NiSi layer. The dopant is allowed to be heated with the NixSi layer together during the second thermal process to form a Si/NiSi2/NiSi interface which may reduce SBH and improve series resistance to obtain a semiconductor device having an excellent performance.
    Type: Application
    Filed: March 20, 2012
    Publication date: July 19, 2012
    Inventors: Yi-Wei Chen, Nien-Ting Ho, Kuo-Chih Lai, Chien-Chung Huang
  • Patent number: 8163607
    Abstract: In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a NixSi layer at meddle height down to a front thereof, or before formation of the NixSi layer, located in a region ranging from a silicon layer at a depth ranging from a half of a predetermined thickness of a NiSi layer down to a depth where is a predetermined front of the NiSi layer. The dopant is allowed to be heated with the NixSi layer together during the second thermal process to form a Si/NiSi2/NiSi interface which may reduce SBH and improve series resistance to obtain a semiconductor device having an excellent performance.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: April 24, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Wei Chen, Nien-Ting Ho, Kuo-Chih Lai, Chien-Chung Huang
  • Publication number: 20120088345
    Abstract: A method for forming silicide is provided. First, a substrate is provided. Second, a gate structure is formed on the substrate which includes a silicon layer, a gate dielectric layer and at least one spacer. Then, a pair of source and drain is formed in the substrate and adjacent to the gate structure. Later, an interlayer dielectric layer is formed to cover the gate structure, the source and the drain. Afterwards, the interlayer dielectric layer is selectively removed to expose the gate structure. Next, multiple contact holes are formed in the interlayer dielectric layer to expose part of the substrate. Afterwards, the exposed substrate is converted to form silicide.
    Type: Application
    Filed: October 12, 2010
    Publication date: April 12, 2012
    Inventors: Yi-Wei Chen, Kuo-Chih Lai, Nien-Ting Ho, Chien-Chung Huang
  • Patent number: 8067281
    Abstract: A method of fabricating a CMOS device is provided. First, first and second gates, first and second offset spacers and first and second lightly-doped regions are respectively formed in first and second type metal-oxide-semiconductor regions. A mask layer is respectively formed on the first and second gates. Next, an epitaxial layer is formed in the substrate on two sides of the second gate. Next, first and second spacers, first and second doped regions are formed. Next, a portion of the first spacer is removed to expose a portion of a surface of the first lightly-doped region, thereby forming a first slimmed spacer. Next, a coating layer containing silicon is formed to cover the exposed first lightly-doped region, the first and second doped regions. Next, the mask layer is removed. Next, a metal silicide layer is formed on the first and second gates and the silicon layer.
    Type: Grant
    Filed: July 5, 2010
    Date of Patent: November 29, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Wei Chen, Chien-Chung Huang, Nien-Ting Ho, Kuo-Chih Lai
  • Publication number: 20110266596
    Abstract: In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a NixSi layer at meddle height down to a front thereof, or before formation of the NixSi layer, located in a region ranging from a silicon layer at a depth ranging from a half of a predetermined thickness of a NiSi layer down to a depth where is a predetermined front of the NiSi layer. The dopant is allowed to be heated with the NixSi layer together during the second thermal process to form a Si/NiSi2/NiSi interface which may reduce SBH and improve series resistance to obtain a semiconductor device having an excellent performance.
    Type: Application
    Filed: April 29, 2010
    Publication date: November 3, 2011
    Inventors: Yi-Wei Chen, Nien-Ting Ho, Kuo-Chih Lai, Chien-Chung Huang
  • Publication number: 20110147948
    Abstract: A structure of a porous low-k layer is described, comprising a bottom portion and a body portion of the same atomic composition, wherein the body portion is located on the bottom portion, and the bottom portion has a density higher than the density of the body portion. An interconnect structure is also described, including the above porous low-k layer, and a conductive layer filling up a damascene opening in the porous low-k layer.
    Type: Application
    Filed: March 2, 2011
    Publication date: June 23, 2011
    Applicant: United Microelectronics Corp.
    Inventors: Mei-Ling Chen, Kuo-Chih Lai, Su-Jen Sung, Chien-Chung Huang, Yu-Tsung Lai
  • Patent number: 7947565
    Abstract: A method of forming a porous low-k layer is described. A CVD process is conducted to a substrate, wherein a framework precursor and a porogen precursor are supplied. In an end period of the supply of the framework precursor, the value of at least one deposition parameter negatively correlated with the density of the product of the CVD process is decreased.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: May 24, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Mei-Ling Chen, Kuo-Chih Lai, Su-Jen Sung, Chien-Chung Huang, Yu-Tsung Lai
  • Patent number: 7943512
    Abstract: A method for fabricating a metal silicide film is described. After providing a silicon material layer, a metal alloy layer is formed to cover the silicon material layer. A thermal process is performed to form a metal alloy silicide layer in a self-aligned way. A wet etching process is performed by using a cleaning solution including sulfuric acid and hydrogen peroxide to remove the residual metals and unreacted metal alloy.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: May 17, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Wei Chen, Kuo-Chih Lai, Nien-Ting Ho
  • Publication number: 20110065245
    Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate and a source/drain region in the semiconductor substrate adjacent to two sides of the gate structure; covering a stress layer on the gate structure and the source/drain region; etching away the stress layer to form a plurality of openings with larger top and smaller bottom to expose surface of the gate structure and the source/drain region; forming a metal layer in the openings; and using the stress layer as a salicide block to react the metal layer with the gate structure and the source/drain region for forming a plurality of silicide layers.
    Type: Application
    Filed: September 13, 2009
    Publication date: March 17, 2011
    Inventors: Jei-Ming Chen, Kuo-Chih Lai, Teng-Chun Tsai, Hsiu-Lien Liao
  • Patent number: 7803702
    Abstract: A method for fabricating metal-oxide transistors is disclosed. First, a semiconductor substrate having a gate structure is provided, in which the gate structure includes a gate dielectric layer and a gate. A source/drain region is formed in the semiconductor substrate, and a cleaning step is performed to fully remove native oxides from the surface of the semiconductor substrate. An oxidation process is conducted to form an oxide layer on the semiconductor substrate and the oxide layer is then treated with fluorine-containing plasma to form a fluorine-containing layer on the surface of the semiconductor substrate. A metal layer is deposited on the semiconductor substrate thereafter and a thermal treatment is performed to transform the metal layer into a silicide layer.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: September 28, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Kuo-Chih Lai, Yi-Wei Chen, Nien-Ting Ho, Teng-Chun Tsai
  • Patent number: 7670438
    Abstract: A method of removing particles from a wafer is provided. The method is adopted after a process for removing unreactive metal of a salicide process or after a salicide process and having oxide residue remaining on a wafer or after a chemical vapor deposition (CVD) process that resulted with particles on a wafer. The method includes performing at least two cycles (stages) of intermediate rinse process. Each cycle of the intermediate rinse process includes conducting a procedure of rotating the wafer at a high speed first, and then conducting a procedure of rotating the wafer at a low speed.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: March 2, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Wei Chen, Bao-Tzeng Huang, An-Chi Liu, Chao-Ching Hsieh, Nien-Ting Ho, Kuo-Chih Lai
  • Publication number: 20100035401
    Abstract: A method for fabricating metal-oxide transistors is disclosed. First, a semiconductor substrate having a gate structure is provided, in which the gate structure includes a gate dielectric layer and a gate. A source/drain region is formed in the semiconductor substrate, and a cleaning step is performed to fully remove native oxides from the surface of the semiconductor substrate. An oxidation process is conducted to form an oxide layer on the semiconductor substrate and the oxide layer is then treated with fluorine-containing plasma to form a fluorine-containing layer on the surface of the semiconductor substrate. A metal layer is deposited on the semiconductor substrate thereafter and a thermal treatment is performed to transform the metal layer into a silicide layer.
    Type: Application
    Filed: August 11, 2008
    Publication date: February 11, 2010
    Inventors: Kuo-Chih Lai, Yi-Wei Chen, Nien-Ting Ho, Teng-Chun Tsai
  • Publication number: 20090275211
    Abstract: A method for fabricating a porous low-k dielectric film includes providing a substrate, performing a first CVD process by providing a back-bone precursor to form an interface dielectric layer, performing a second CVD process by providing a porogen precursor to form a back-bone layer, and removing the porogen material in the back-bone layer so that the back-bone layer becomes an ultra low-k dielectric layer. The interface dielectric layer and the ultra low-k dielectric layer compose a porous low-k dielectric film.
    Type: Application
    Filed: July 15, 2009
    Publication date: November 5, 2009
    Inventors: Mei-Ling Chen, Su-Jen Sung, Kuo-Chih Lai, Jei-Ming Chen
  • Publication number: 20090191714
    Abstract: The present invention provides a method of removing oxides. First, a substrate having the oxides is loaded into a reaction chamber, which includes a susceptor setting in the bottom portion of the chamber, a shower head setting above the susceptor, and a heater setting above the susceptor. Subsequently, an etching process is performed. A first thermal treatment process is then carried out. Finally, a second thermal treatment process is carried out, and a reaction temperature of the second thermal treatment process is higher than a reaction temperature of the first thermal treatment process.
    Type: Application
    Filed: January 24, 2008
    Publication date: July 30, 2009
    Inventors: Kuo-Chih Lai, Yi-Wei Chen, Nien-Ting Ho, Teng-Chun Tsai
  • Publication number: 20090155999
    Abstract: A method for fabricating a metal silicide film is described. After providing a silicon material layer, a metal alloy layer is formed to cover the silicon material layer. A thermal process is performed to form a metal alloy silicide layer in a self-aligned way. A wet etching process is performed by using a cleaning solution including sulfuric acid and hydrogen peroxide to remove the residual metals and unreacted metal alloy.
    Type: Application
    Filed: December 13, 2007
    Publication date: June 18, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Wei Chen, Kuo-Chih Lai, Nien-Ting Ho