Patents by Inventor Kuo-Chih Lai
Kuo-Chih Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130078800Abstract: A method for fabricating metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate having a silicide thereon; performing a first rapid thermal process to drive-in platinum from a surface of the silicide into the silicide; and removing un-reacted platinum in the first rapid thermal process.Type: ApplicationFiled: September 28, 2011Publication date: March 28, 2013Inventors: Kuo-Chih Lai, Nien-Ting Ho, Shu Min Huang, Bor-Shyang Liao, Chia Chang Hsu
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Publication number: 20130023098Abstract: A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.Type: ApplicationFiled: July 18, 2011Publication date: January 24, 2013Inventors: Po-Cheng Huang, Kuo-Chih Lai, Ching-I Li, Yu-Shu Lin, Ya-Jyuan Hung, Yen-Liang Lu, Yu-Wen Wang, Hsin-Chih Yu
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Publication number: 20130014779Abstract: A cleaning method of a semiconductor manufacturing process is provided. The cleaning method is applied to a semiconductor component including a plurality of material layers formed thereon. An opening is defined in the material layers, and a side wall is exposed from the opening The side wall at least includes a first material layer and a second material layer. At first, a first cleaning process is performed till a lateral etched thickness of the first material layer is equal to a lateral etched thickness of the second material layer. Then, a byproduct formed in the first cleaning process is removed.Type: ApplicationFiled: July 13, 2011Publication date: January 17, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-Wei CHEN, Teng-Chun TSAI, Kuo-Chih LAI, Shu-Min HUANG
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Patent number: 8350246Abstract: A structure of a porous low-k layer is described, comprising a bottom portion and a body portion of the same atomic composition, wherein the body portion is located on the bottom portion, and the bottom portion has a density higher than the density of the body portion. An interconnect structure is also described, including the above porous low-k layer, and a conductive layer filling up a damascene opening in the porous low-k layer.Type: GrantFiled: March 2, 2011Date of Patent: January 8, 2013Assignee: United Microelectronics Corp.Inventors: Mei-Ling Chen, Kuo-Chih Lai, Su-Jen Sung, Chien-Chung Huang, Yu-Tsung Lai
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Patent number: 8344465Abstract: In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a NixSi layer at middle height down to a front thereof, or before formation of the NixSi layer, located in a region ranging from a silicon layer at a depth ranging from a half of a predetermined thickness of a NiSi layer down to a depth where is a predetermined front of the NiSi layer. The dopant is allowed to be heated with the NixSi layer together during the second thermal process to form a Si/NiSi2/NiSi interface which may reduce SBH and improve series resistance to obtain a semiconductor device having an excellent performance.Type: GrantFiled: March 20, 2012Date of Patent: January 1, 2013Assignee: United Microelectronics Corp.Inventors: Yi-Wei Chen, Nien-Ting Ho, Kuo-Chih Lai, Chien-Chung Huang
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Publication number: 20120181635Abstract: In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a NixSi layer at meddle height down to a front thereof, or before formation of the NixSi layer, located in a region ranging from a silicon layer at a depth ranging from a half of a predetermined thickness of a NiSi layer down to a depth where is a predetermined front of the NiSi layer. The dopant is allowed to be heated with the NixSi layer together during the second thermal process to form a Si/NiSi2/NiSi interface which may reduce SBH and improve series resistance to obtain a semiconductor device having an excellent performance.Type: ApplicationFiled: March 20, 2012Publication date: July 19, 2012Inventors: Yi-Wei Chen, Nien-Ting Ho, Kuo-Chih Lai, Chien-Chung Huang
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Patent number: 8163607Abstract: In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a NixSi layer at meddle height down to a front thereof, or before formation of the NixSi layer, located in a region ranging from a silicon layer at a depth ranging from a half of a predetermined thickness of a NiSi layer down to a depth where is a predetermined front of the NiSi layer. The dopant is allowed to be heated with the NixSi layer together during the second thermal process to form a Si/NiSi2/NiSi interface which may reduce SBH and improve series resistance to obtain a semiconductor device having an excellent performance.Type: GrantFiled: April 29, 2010Date of Patent: April 24, 2012Assignee: United Microelectronics Corp.Inventors: Yi-Wei Chen, Nien-Ting Ho, Kuo-Chih Lai, Chien-Chung Huang
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Publication number: 20120088345Abstract: A method for forming silicide is provided. First, a substrate is provided. Second, a gate structure is formed on the substrate which includes a silicon layer, a gate dielectric layer and at least one spacer. Then, a pair of source and drain is formed in the substrate and adjacent to the gate structure. Later, an interlayer dielectric layer is formed to cover the gate structure, the source and the drain. Afterwards, the interlayer dielectric layer is selectively removed to expose the gate structure. Next, multiple contact holes are formed in the interlayer dielectric layer to expose part of the substrate. Afterwards, the exposed substrate is converted to form silicide.Type: ApplicationFiled: October 12, 2010Publication date: April 12, 2012Inventors: Yi-Wei Chen, Kuo-Chih Lai, Nien-Ting Ho, Chien-Chung Huang
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Patent number: 8067281Abstract: A method of fabricating a CMOS device is provided. First, first and second gates, first and second offset spacers and first and second lightly-doped regions are respectively formed in first and second type metal-oxide-semiconductor regions. A mask layer is respectively formed on the first and second gates. Next, an epitaxial layer is formed in the substrate on two sides of the second gate. Next, first and second spacers, first and second doped regions are formed. Next, a portion of the first spacer is removed to expose a portion of a surface of the first lightly-doped region, thereby forming a first slimmed spacer. Next, a coating layer containing silicon is formed to cover the exposed first lightly-doped region, the first and second doped regions. Next, the mask layer is removed. Next, a metal silicide layer is formed on the first and second gates and the silicon layer.Type: GrantFiled: July 5, 2010Date of Patent: November 29, 2011Assignee: United Microelectronics Corp.Inventors: Yi-Wei Chen, Chien-Chung Huang, Nien-Ting Ho, Kuo-Chih Lai
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Publication number: 20110266596Abstract: In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a NixSi layer at meddle height down to a front thereof, or before formation of the NixSi layer, located in a region ranging from a silicon layer at a depth ranging from a half of a predetermined thickness of a NiSi layer down to a depth where is a predetermined front of the NiSi layer. The dopant is allowed to be heated with the NixSi layer together during the second thermal process to form a Si/NiSi2/NiSi interface which may reduce SBH and improve series resistance to obtain a semiconductor device having an excellent performance.Type: ApplicationFiled: April 29, 2010Publication date: November 3, 2011Inventors: Yi-Wei Chen, Nien-Ting Ho, Kuo-Chih Lai, Chien-Chung Huang
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Publication number: 20110147948Abstract: A structure of a porous low-k layer is described, comprising a bottom portion and a body portion of the same atomic composition, wherein the body portion is located on the bottom portion, and the bottom portion has a density higher than the density of the body portion. An interconnect structure is also described, including the above porous low-k layer, and a conductive layer filling up a damascene opening in the porous low-k layer.Type: ApplicationFiled: March 2, 2011Publication date: June 23, 2011Applicant: United Microelectronics Corp.Inventors: Mei-Ling Chen, Kuo-Chih Lai, Su-Jen Sung, Chien-Chung Huang, Yu-Tsung Lai
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Patent number: 7947565Abstract: A method of forming a porous low-k layer is described. A CVD process is conducted to a substrate, wherein a framework precursor and a porogen precursor are supplied. In an end period of the supply of the framework precursor, the value of at least one deposition parameter negatively correlated with the density of the product of the CVD process is decreased.Type: GrantFiled: February 7, 2007Date of Patent: May 24, 2011Assignee: United Microelectronics Corp.Inventors: Mei-Ling Chen, Kuo-Chih Lai, Su-Jen Sung, Chien-Chung Huang, Yu-Tsung Lai
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Patent number: 7943512Abstract: A method for fabricating a metal silicide film is described. After providing a silicon material layer, a metal alloy layer is formed to cover the silicon material layer. A thermal process is performed to form a metal alloy silicide layer in a self-aligned way. A wet etching process is performed by using a cleaning solution including sulfuric acid and hydrogen peroxide to remove the residual metals and unreacted metal alloy.Type: GrantFiled: December 13, 2007Date of Patent: May 17, 2011Assignee: United Microelectronics Corp.Inventors: Yi-Wei Chen, Kuo-Chih Lai, Nien-Ting Ho
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Publication number: 20110065245Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate and a source/drain region in the semiconductor substrate adjacent to two sides of the gate structure; covering a stress layer on the gate structure and the source/drain region; etching away the stress layer to form a plurality of openings with larger top and smaller bottom to expose surface of the gate structure and the source/drain region; forming a metal layer in the openings; and using the stress layer as a salicide block to react the metal layer with the gate structure and the source/drain region for forming a plurality of silicide layers.Type: ApplicationFiled: September 13, 2009Publication date: March 17, 2011Inventors: Jei-Ming Chen, Kuo-Chih Lai, Teng-Chun Tsai, Hsiu-Lien Liao
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Patent number: 7803702Abstract: A method for fabricating metal-oxide transistors is disclosed. First, a semiconductor substrate having a gate structure is provided, in which the gate structure includes a gate dielectric layer and a gate. A source/drain region is formed in the semiconductor substrate, and a cleaning step is performed to fully remove native oxides from the surface of the semiconductor substrate. An oxidation process is conducted to form an oxide layer on the semiconductor substrate and the oxide layer is then treated with fluorine-containing plasma to form a fluorine-containing layer on the surface of the semiconductor substrate. A metal layer is deposited on the semiconductor substrate thereafter and a thermal treatment is performed to transform the metal layer into a silicide layer.Type: GrantFiled: August 11, 2008Date of Patent: September 28, 2010Assignee: United Microelectronics Corp.Inventors: Kuo-Chih Lai, Yi-Wei Chen, Nien-Ting Ho, Teng-Chun Tsai
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Patent number: 7670438Abstract: A method of removing particles from a wafer is provided. The method is adopted after a process for removing unreactive metal of a salicide process or after a salicide process and having oxide residue remaining on a wafer or after a chemical vapor deposition (CVD) process that resulted with particles on a wafer. The method includes performing at least two cycles (stages) of intermediate rinse process. Each cycle of the intermediate rinse process includes conducting a procedure of rotating the wafer at a high speed first, and then conducting a procedure of rotating the wafer at a low speed.Type: GrantFiled: October 3, 2007Date of Patent: March 2, 2010Assignee: United Microelectronics Corp.Inventors: Yi-Wei Chen, Bao-Tzeng Huang, An-Chi Liu, Chao-Ching Hsieh, Nien-Ting Ho, Kuo-Chih Lai
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Publication number: 20100035401Abstract: A method for fabricating metal-oxide transistors is disclosed. First, a semiconductor substrate having a gate structure is provided, in which the gate structure includes a gate dielectric layer and a gate. A source/drain region is formed in the semiconductor substrate, and a cleaning step is performed to fully remove native oxides from the surface of the semiconductor substrate. An oxidation process is conducted to form an oxide layer on the semiconductor substrate and the oxide layer is then treated with fluorine-containing plasma to form a fluorine-containing layer on the surface of the semiconductor substrate. A metal layer is deposited on the semiconductor substrate thereafter and a thermal treatment is performed to transform the metal layer into a silicide layer.Type: ApplicationFiled: August 11, 2008Publication date: February 11, 2010Inventors: Kuo-Chih Lai, Yi-Wei Chen, Nien-Ting Ho, Teng-Chun Tsai
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Publication number: 20090275211Abstract: A method for fabricating a porous low-k dielectric film includes providing a substrate, performing a first CVD process by providing a back-bone precursor to form an interface dielectric layer, performing a second CVD process by providing a porogen precursor to form a back-bone layer, and removing the porogen material in the back-bone layer so that the back-bone layer becomes an ultra low-k dielectric layer. The interface dielectric layer and the ultra low-k dielectric layer compose a porous low-k dielectric film.Type: ApplicationFiled: July 15, 2009Publication date: November 5, 2009Inventors: Mei-Ling Chen, Su-Jen Sung, Kuo-Chih Lai, Jei-Ming Chen
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Publication number: 20090191714Abstract: The present invention provides a method of removing oxides. First, a substrate having the oxides is loaded into a reaction chamber, which includes a susceptor setting in the bottom portion of the chamber, a shower head setting above the susceptor, and a heater setting above the susceptor. Subsequently, an etching process is performed. A first thermal treatment process is then carried out. Finally, a second thermal treatment process is carried out, and a reaction temperature of the second thermal treatment process is higher than a reaction temperature of the first thermal treatment process.Type: ApplicationFiled: January 24, 2008Publication date: July 30, 2009Inventors: Kuo-Chih Lai, Yi-Wei Chen, Nien-Ting Ho, Teng-Chun Tsai
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Publication number: 20090155999Abstract: A method for fabricating a metal silicide film is described. After providing a silicon material layer, a metal alloy layer is formed to cover the silicon material layer. A thermal process is performed to form a metal alloy silicide layer in a self-aligned way. A wet etching process is performed by using a cleaning solution including sulfuric acid and hydrogen peroxide to remove the residual metals and unreacted metal alloy.Type: ApplicationFiled: December 13, 2007Publication date: June 18, 2009Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-Wei Chen, Kuo-Chih Lai, Nien-Ting Ho