Patents by Inventor Kuo-Chio Liu

Kuo-Chio Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120313
    Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Inventors: Sheng-Yao YANG, Ling-Wei LI, Yu-Jui WU, Cheng-Lin HUANG, Chien-Chen LI, Lieh-Chuan CHEN, Che-Jung CHU, Kuo-Chio LIU
  • Patent number: 11923353
    Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jen Lai, Chung-Yi Lin, Hsi-Kuei Cheng, Chen-Shien Chen, Kuo-Chio Liu
  • Publication number: 20230411307
    Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes a large package component, such as a CoWoS, adhered to a large package substrate, such as a printed circuit board, an underfill material disposed between the large package component and the large package substrate, and a stress-release structure with high elongation values formed from photolithography encapsulated by the underfill material. The stress-release structure helping to reduce stress in the underfill material to reduce the risk of underfill cracking caused by the difference in coefficients of thermal expansion between the large package component and the large package substrate.
    Type: Application
    Filed: June 15, 2022
    Publication date: December 21, 2023
    Inventors: Wen-Yi Lin, Kuang-Chun Lee, Chien-Chen Li, Chien-Li Kuo, Kuo-Chio Liu
  • Patent number: 11848302
    Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive bump over and electrically connected to the chip. The chip package structure includes a ring-like structure over and electrically insulated from the chip. The ring-like structure surrounds the conductive bump, and the ring-like structure and the conductive bump are made of a same material.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Yao Yang, Ling-Wei Li, Yu-Jui Wu, Cheng-Lin Huang, Chien-Chen Li, Lieh-Chuan Chen, Che-Jung Chu, Kuo-Chio Liu
  • Publication number: 20230395461
    Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes a package component with one or more integrated circuits adhered to a package substrate, a hybrid thermal interface material utilizing a combination of polymer based material with high elongation values and metal based material with high thermal conductivity values. The polymer based thermal interface material placed on the edge of the package component contains the metal based thermal interface material in liquid form.
    Type: Application
    Filed: June 6, 2022
    Publication date: December 7, 2023
    Inventors: Wen-Yi Lin, Kuang-Chun Lee, Chien-Chen Li, Chien-Li Kuo, Kuo-Chio Liu
  • Publication number: 20230387101
    Abstract: In an embodiment, a method of forming an integrated circuit package includes: attaching a first carrier to a package component, the package component comprising: an interposer; a first semiconductor die attached to a first side of the interposer; a second semiconductor die attached to the first side of the interposer; an encapsulant encapsulating the first semiconductor die and the second semiconductor die; and conductive connectors attached to a second side of the interposer; attaching a second carrier to a package substrate, the package substrate comprising bond pads; bonding the conductive connectors of the package component to the bond pads of the package substrate by reflowing the conductive connectors while the first carrier is attached to the package component and while the second carrier is attached to the package substrate; removing the first carrier; and removing the second carrier.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 30, 2023
    Inventors: Pei-Haw Tsao, Chien-Li Kuo, Kuo-Chio Liu
  • Publication number: 20230377905
    Abstract: In an embodiment, a device includes: an integrated circuit die including a die connector; a first through via adjacent the integrated circuit die; an encapsulant encapsulating the first through via and the integrated circuit die; and a redistribution structure on the encapsulant, the redistribution structure including a redistribution line, the redistribution line physically and electrically coupled to the die connector of the integrated circuit die, the redistribution line electrically isolated from the first through via, the redistribution line crossing over the first through via.
    Type: Application
    Filed: May 23, 2022
    Publication date: November 23, 2023
    Applicants: Taiwan Semiconductor Manufacturing Co., Ltd., Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Li Kuo, Chien-Chen Li, Kuo-Chio Liu, Kuang-Chun Lee, Wen-Yi Lin
  • Publication number: 20230369152
    Abstract: A package includes a die, first conductive structures, second conductive structures, and an encapsulant. The die has a rear surface. The first conductive structures and the second conductive structures surround the die. The first conductive structures include cylindrical columns and the second conductive structures include elliptical columns. At least one of the second conductive structures is closer to the die than the first conductive structures. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures.
    Type: Application
    Filed: July 21, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Huan Chiu, Chun-Jen Chen, Chen-Shien Chen, Kuo-Chio Liu, Kuo-Hui Chang, Chung-Yi Lin, Hsi-Kuei Cheng, Yi-Jen Lai
  • Patent number: 11756849
    Abstract: A package includes a die, first conductive structures, second conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The first conductive structures and the second conductive structures surround the die. A shape of the first conductive structures is different a shape of the second conductive structures. The second conductive structures include elliptical columns having straight sidewalls. A distance between the first conductive structure that is closest to the die and the die is greater than a distance between the second conductive structure that is closest to the die and the die. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures. The redistribution structure is over the die and the encapsulant. The redistribution structure is electrically connected to the die, the first conductive structures, and the second conductive structures.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Huan Chiu, Chun-Jen Chen, Chen-Shien Chen, Kuo-Chio Liu, Kuo-Hui Chang, Chung-Yi Lin, Hsi-Kuei Cheng, Yi-Jen Lai
  • Publication number: 20230113265
    Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive bump over and electrically connected to the chip. The chip package structure includes a ring-like structure over and electrically insulated from the chip. The ring-like structure surrounds the conductive bump, and the ring-like structure and the conductive bump are made of a same material.
    Type: Application
    Filed: December 13, 2022
    Publication date: April 13, 2023
    Inventors: Sheng-Yao YANG, Ling-Wei LI, Yu-Jui WU, Cheng-Lin HUANG, Chien-Chen LI, Lieh-Chuan CHEN, Che-Jung CHU, Kuo-Chio LIU
  • Patent number: 11594484
    Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mirng-Ji Lii, Chung-Shi Liu, Chin-Yu Ku, Hung-Jui Kuo, Alexander Kalnitsky, Ming-Che Ho, Yi-Wen Wu, Ching-Hui Chen, Kuo-Chio Liu
  • Patent number: 11545463
    Abstract: A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: January 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Yao Yang, Ling-Wei Li, Yu-Jui Wu, Cheng-Lin Huang, Chien-Chen Li, Lieh-Chuan Chen, Che-Jung Chu, Kuo-Chio Liu
  • Publication number: 20220399325
    Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.
    Type: Application
    Filed: July 27, 2022
    Publication date: December 15, 2022
    Inventors: Yi-Jen Lai, Chung-Yi Lin, Hsi-Kuei Cheng, Chen-Shien Chen, Kuo-Chio Liu
  • Publication number: 20220367398
    Abstract: Package structures and methods for manufacturing the same are provided. The package structure includes a first bump structure formed over a first substrate. The first bump structure includes a first pillar layer formed over the first substrate and a first barrier layer formed over the first pillar layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first edge of the first pillar layer. The package structure further includes a second bump structure bonded to the first bump structure through a solder joint. In addition, the second bump structure includes a second pillar layer formed over a second substrate and a second barrier layer formed over the second pillar layer. The first protruding portion of the first barrier layer is spaced apart from the solder joint.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hung CHEN, Yu-Nu HSU, Chun-Chen LIU, Heng-Chi HUANG, Chien-Chen LI, Shih-Yen CHEN, Cheng-Nan HSIEH, Kuo-Chio LIU, Chen-Shien CHEN, Chin-Yu KU, Te-Hsun PANG, Yuan-Feng WU, Sen-Chi CHIANG
  • Patent number: 11469203
    Abstract: A method for forming a package structure includes forming an under bump metallization (UBM) layer over a metal pad and forming a photoresist layer over the UBM layer. The method further includes patterning the photoresist layer to form an opening in the photoresist layer. The method also includes forming a first bump structure over the first portion of the UBM layer. The first bump structure includes a first barrier layer over a first pillar layer. The method includes placing a second bump structure over the first bump structure. The second bump structure includes a second barrier layer over a second pillar layer. The method further includes reflowing the first bump structure and the second bump structure to form a solder joint between a first inter intermetallic compound (IMC) and a second IMC.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: October 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hung Chen, Yu-Nu Hsu, Chun-Chen Liu, Heng-Chi Huang, Chien-Chen Li, Shih-Yen Chen, Cheng-Nan Hsieh, Kuo-Chio Liu, Chen-Shien Chen, Chin-Yu Ku, Te-Hsun Pang, Yuan-Feng Wu, Sen-Chi Chiang
  • Publication number: 20220301964
    Abstract: A package includes a die, first conductive structures, second conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The first conductive structures and the second conductive structures surround the die. A shape of the first conductive structures is different a shape of the second conductive structures. The second conductive structures include elliptical columns having straight sidewalls. A distance between the first conductive structure that is closest to the die and the die is greater than a distance between the second conductive structure that is closest to the die and the die. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures. The redistribution structure is over the die and the encapsulant. The redistribution structure is electrically connected to the die, the first conductive structures, and the second conductive structures.
    Type: Application
    Filed: June 8, 2022
    Publication date: September 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Huan Chiu, Chun-Jen Chen, Chen-Shien Chen, Kuo-Chio Liu, Kuo-Hui Chang, Chung-Yi Lin, Hsi-Kuei Cheng, Yi-Jen Lai
  • Patent number: 11437361
    Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Jen Lai, Lin Chung-Yi, Hsi-Kuei Cheng, Chen-Shien Chen, Kuo-Chio Liu
  • Patent number: 11404341
    Abstract: A package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The conductive structures include elliptical columns. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is over the active surface of the die and the encapsulant. The redistribution structure is electrically connected to the die and the conductive structures.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Huan Chiu, Chun-Jen Chen, Chen-Shien Chen, Kuo-Chio Liu, Kuo-Hui Chang, Chung-Yi Lin, Hsi-Kuei Cheng, Yi-Jen Lai
  • Publication number: 20220173083
    Abstract: A package on package structure includes a first package, a plurality of conductive bumps, a second package and an underfill. The conductive bumps are disposed on a second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps, and includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. A shortest distance from an upper surface of the encapsulating material to an upper surface of the semiconductor device is greater than or substantially equal to twice a thickness of the semiconductor device. The underfill is filled between the first package and the second package.
    Type: Application
    Filed: February 16, 2022
    Publication date: June 2, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dong-Han Shen, Chen-Shien Chen, Kuo-Chio Liu, Hsi-Kuei Cheng, Yi-Jen Lai
  • Patent number: 11257797
    Abstract: A package on package structure includes a first package, a plurality of conductive bumps, a second package and an underfill. The conductive bumps are disposed on a second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps, and includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. A shortest distance from an upper surface of the encapsulating material to an upper surface of the semiconductor device is greater than or substantially equal to twice a thickness of the semiconductor device. The underfill is filled between the first package and the second package.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dong-Han Shen, Chen-Shien Chen, Kuo-Chio Liu, Hsi-Kuei Cheng, Yi-Jen Lai