Patents by Inventor Kuo-Chou Chen

Kuo-Chou Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942543
    Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Chen-Chien Chang, Chih-Yuan Chan, Kuo-Ming Wu, Chun-Lin Tsai
  • Patent number: 9127356
    Abstract: A sputtering target is provided that includes a planar backing plate and a target material formed over the planar backing plate and including an uneven sputtering surface including thick portions and thin portions and configured in conjunction with a sputtering apparatus such as a magnetron sputtering tool with a fixed magnet arrangement. The uneven surface is designed in conjunction with the magnetic fields that will be produced by the magnet arrangement such that the thicker target portions are positioned at locations where target erosion occurs at a high rate. Also provided is the magnetron sputtering system and a method for utilizing the target with uneven sputtering surface such that the thickness across the target to become more uniform in time as the target is used.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: September 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Liang Chueh, Kuo-Chou Chen, Ren-Dou Lee, Hsien-Liang Meng, Chun-Wei Lin
  • Publication number: 20130043120
    Abstract: A sputtering target is provided that includes a planar backing plate and a target material formed over the planar backing plate and including an uneven sputtering surface including thick portions and thin portions and configured in conjunction with a sputtering apparatus such as a magnetron sputtering tool with a fixed magnet arrangement. The uneven surface is designed in conjunction with the magnetic fields that will be produced by the magnet arrangement such that the thicker target portions are positioned at locations where target erosion occurs at a high rate. Also provided is the magnetron sputtering system and a method for utilizing the target with uneven sputtering surface such that the thickness across the target to become more uniform in time as the target is used.
    Type: Application
    Filed: August 18, 2011
    Publication date: February 21, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Liang CHUEH, Kuo-Chou CHEN, Ren-Dou LEE, Hsien-Liang MENG, Chun-Wei LIN
  • Publication number: 20040110365
    Abstract: A method of forming a planarized bond pad structure in a bond pad opening, while removing bond pad material from an opening in a non-device region used for scribe line formation, has been developed. A first iteration of this invention features the formation of the planarized bond bad structure in a bond pad opening defined in a dielectric layer, accomplished via deposition of a bond pad material followed by a chemical mechanical polishing (CMP), procedure, with the CMP procedure terminating at the top surface of the dielectric stop layer. The above procedures also result in unwanted bond pad material remaining in the scribe line opening. A photolithographic procedure defined to protect the planarized bond pad structure is used with a selective etching procedure removing unwanted bond pad material from the scribe line opening.
    Type: Application
    Filed: December 10, 2002
    Publication date: June 10, 2004
    Applicant: Taiwan Semiconductor Manufacturing Company
    Inventors: Yea-Zan Su, Cheng-Chung Huang, Tien-Chi Wu, Kuo-Chou Chen
  • Patent number: 6709965
    Abstract: A process for forming a bond pad structure to be used to accommodate a subsequent wire bond, has been developed. The process features defining a bond pad opening in a composite insulator stack, exposing a portion of a top surface of an upper level metal interconnect structure at the bottom of the bond pad opening. The bond pad opening is formed with a top portion of the composite insulator stack laterally pulled back from a bottom portion of the same composite insulator stack. The bond pad structure, comprised of aluminum—copper, is then formed entirely in the bond pad opening, with the top surface of the bond pad structure lower than the top surface of the composite insulator stack, thus resulting in a bond pad structure topography offering reduced risk of damage during subsequent pre-wire bonding procedures.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: March 23, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Kuo-Chou Chen, Huai-Jen Hsu