Abstract: A semiconductor device includes a plurality of interlayer dielectric layers, a memory cell, and a first capping layer. The memory cell is embedded in the interlayer dielectric layers, the first capping layer covers the memory cell and surrounds the sidewalls of the memory cell, the first capping layer includes a hydrogen absorbing material, and the hydrogen absorbing material prevents hydrogen gas from entering the memory cell.

Abstract: A lithography system includes an immersion lithographic apparatus, a fluid supply device, and a sensor. The fluid supply is configured to supply fluid to the immersion lithographic apparatus. The fluid supply device includes at least one liquid storage tank, an upper liquid pipe and a lower liquid pipe connected to the liquid storage tank. The sensor includes at least one hydraulic pressure gauge. The at least one hydraulic pressure gauge is arranged near a lower part of the liquid storage tank and connected to the lower liquid pipe and the upper liquid pipe so as to measure the hydraulic pressure at a bottom of the liquid storage tank. The height of the liquid level in the liquid storage tank is calculated from the hydraulic pressure.

Abstract: A semiconductor device is provided, which includes a first semiconductor structure, a second semiconductor structure, and an active region. The active region is located between the first semiconductor structure and the second semiconductor structure. The active region includes a light-emitting region having N pair(s) of semiconductor stack(s). Each of the semiconductor stack includes a well layer and a barrier layer, in which N is a positive integer greater than or equal to 1. The well layer includes a first group III-V semiconductor material including indium with a first percentage of indium content. The barrier layer includes a second group III-V semiconductor material including indium with a second percentage of indium content. The first group III-V semiconductor material and the second group III-V semiconductor material further includes phosphorus. The second percentage of indium content is less than the first percentage of indium content.

Abstract: A lithography system includes an immersion lithographic apparatus, a fluid supply device, and a sensor. The fluid supply is configured to supply fluid to the immersion lithographic apparatus. The fluid supply device includes at least one liquid storage tank, an upper liquid pipe and a lower liquid pipe connected to the liquid storage tank. The sensor includes at least one hydraulic pressure gauge. The at least one hydraulic pressure gauge is arranged near a lower part of the liquid storage tank and connected to the lower liquid pipe and the upper liquid pipe so as to measure the hydraulic pressure at a bottom of the liquid storage tank. The height of the liquid level in the liquid storage tank is calculated from the hydraulic pressure.

Abstract: An integrated chip including a reference magnetic layer and a barrier layer over the reference magnetic layer. A first free magnetic layer is over the barrier layer. A second free magnetic layer is over the first free magnetic layer. A spacer layer is between the first free magnetic layer and the second free magnetic layer. The spacer layer includes magnesium and a transition metal. An atomic ratio of the magnesium to the transition metal ranges from 15% to 80%.

Abstract: A semiconductor device is provided, which includes a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first dopant. The second semiconductor structure is located on the first semiconductor structure and includes a second dopant different from the first dopant. The active region includes a plurality of semiconductor pairs and located between the first semiconductor structure and the second semiconductor structure. Each semiconductor pair includes a barrier layer and a well layer and includes the first dopant. The active region does not include a nitrogen element. A doping concentration of the first dopant in the first semiconductor structure is higher than a doping concentration of the first dopant in the active region.

Abstract: A semiconductor device comprises a first semiconductor structure, a second semiconductor structure located on the first semiconductor structure, and an active layer located between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure has a first conductivity type, and includes a plurality of first layers and a plurality of second layers alternately stacked. The second semiconductor structure has a second conductivity type opposite to the first conductivity type. The plurality of first layers and the plurality of second layers include indium and phosphorus, and the plurality of first layers and the plurality of second layers respectively have a first indium atomic percentage and a second indium atomic percentage. The second indium atomic percentage is different from the first indium atomic percentage.

Abstract: A manufacturing method of a memory device are provided. The method includes following steps. A gate stacking structure is formed over a substrate. A first insulating layer, a second insulating layer and a mask material layer are sequentially formed over the substrate to cover the gate stacking structure. An ion implantation process is performed on the mask material layer to form a doped portion in the mask material layer. The doped portion caps on a top portion of the gate stacking structure. A first patterning process is performed on the mask material layer using the doped portion as a shadow mask to remove a bottom portion of the mask material layer extending along a surface of the substrate. A second patterning process is performed to remove the doped portion of the mask material layer and an exposed bottom portion of the second insulating layer surrounding the gate stacking structure.

Abstract: A semiconductor device according to the present disclosure includes a first conductive feature and a second conductive feature in a first dielectric layer, a buffer layer over the first dielectric layer, a second dielectric layer over the buffer layer, a first bottom via extending through the buffer layer and the second dielectric layer, a second bottom via extending through the buffer layer and the second dielectric layer, a first bottom electrode disposed on the first bottom via, a second bottom electrode disposed on the second bottom via, a first magnetic tunnel junction (MTJ) stack over the first bottom electrode, and a second MTJ stack over the second bottom electrode. The first MTJ stack and the second MTJ stack have a same thickness. The first MTJ stack has a first width and the second MTJ stack has a second width greater than the first width.

Abstract: A manufacturing method of a memory device are provided. The method includes following steps. A gate stacking structure is formed over a substrate. A first insulating layer, a second insulating layer and a mask material layer are sequentially formed over the substrate to cover the gate stacking structure. An ion implantation process is performed on the mask material layer to form a doped portion in the mask material layer. The doped portion caps on a top portion of the gate stacking structure. A first patterning process is performed on the mask material layer using the doped portion as a shadow mask to remove a bottom portion of the mask material layer extending along a surface of the substrate. A second patterning process is performed to remove the doped portion of the mask material layer and an exposed bottom portion of the second insulating layer surrounding the gate stacking structure.

Abstract: A semiconductor device is provided, which includes a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first dopant. The second semiconductor structure is located on the first semiconductor structure and includes a second dopant different from the first dopant. The active region includes a plurality of semiconductor pairs and is located between the first semiconductor structure and the second semiconductor structure. One of the plurality of semiconductor pairs has a barrier layer and a well layer and includes the first dopant. The barrier layer has a first thickness and a first Al content, and the well layer has a second thickness and a second Al content, the second thickness is less than the first thickness, and the second Al content is less than the first Al content.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a gate stacking structure, a first insulating layer, a second insulating layer and a first spacer. The gate stacking structure is disposed over a substrate. The first insulating layer covers a top surface and a sidewall of the gate stacking structure. The second insulating layer covers a surface of the first insulating layer. A top corner region of the gate stacking structure is covered by the first and second insulating layers. The first spacer is located on the sidewall of the gate stacking structure, and covers a surface of the second insulating layer. A topmost end of the first spacer is lower than a topmost surface of the second insulating layer.

Abstract: Disclosed methods include placing a semiconductor wafer containing MRAM devices into a first magnetic field that has a magnitude sufficient to magnetically polarize MRAM bits and has a substantially uniform field strength and direction over the entire area of the wafer. The method further includes placing the wafer in a second magnetic field having an opposite field direction, a substantially uniform field strength and direction over the entire area of the wafer, and magnitude less than a design threshold for MRAM bit magnetization reversal. The method further includes determining a presence of malfunctioning MRAM bits by determining that such malfunctioning MRAM bits have a magnetic polarization that was reversed due to exposure to the second magnetic field. Malfunctioning MRAM bits may further be characterized by electrically reading data bits, or by using a chip probe to read one or more of voltage, current, resistances, etc., of the MRAM devices.

Abstract: A semiconductor device is provided, which includes a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first dopant. The second semiconductor structure is located on the first semiconductor structure and includes a second dopant different from the first dopant. The active region includes a plurality of semiconductor pairs and is located between the first semiconductor structure and the second semiconductor structure. One of the plurality of semiconductor pairs has a barrier layer and a well layer and includes the first dopant. The barrier layer has a first thickness and a first Al content, and the well layer has a second thickness and a second Al content, the second thickness is less than the first thickness, and the second Al content is less than the first Al content.

Abstract: The present disclosure relates to a power management system. The power management system comprises a first power supply device, a second power supply device, a power supply control device, a data processing device and a load. The power supply control device is connected to the first power supply device. The data processing device is connected to the first power supply device, the second power supply device and the power supply control device. The load is connected to the first power supply device and the second power supply device. The power supply control device is configured to, when activated, provide a first signal to the data processing device. The data processing device is configured to select the first power supply device or the second power supply device to provide power to the load according to the first signal.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a gate stacking structure, a first insulating layer, a second insulating layer and a first spacer. The gate stacking structure is disposed over a substrate. The first insulating layer covers a top surface and a sidewall of the gate stacking structure. The second insulating layer covers a surface of the first insulating layer. A top corner region of the gate stacking structure is covered by the first and second insulating layers. The first spacer is located on the sidewall of the gate stacking structure, and covers a surface of the second insulating layer. A topmost end of the first spacer is lower than a topmost surface of the second insulating layer.

Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.

Abstract: A light-emitting device is provided. The light-emitting device comprises The light-emitting device comprises a light-emitting stack comprising a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer; and a third semiconductor layer on the light-emitting stack and comprising a first sub-layer, a second sub-layer and a roughened surface, wherein the first sub-layer has the same composition as that of the second sub-layer, and the second sub-layer is farther from the light-emitting stack than the first sub-layer; wherein the first sub-layer and the second sub-layer each comprises a Group III element and a Group V element, and an atomic ratio of the Group III element to the Group V element of the first sub-layer is less than an atomic ratio of the Group III element to the Group V element of the second sub-layer.

Abstract: An optoelectronic device includes a semiconductor stack including a first surface and a second surface opposite to the first surface; a first contact layer on the first surface; and a second contact layer on the second surface. The second contact layer is not overlapped with the first contact layer in a vertical direction. The second contact layer includes a plurality of dots separating to each other and formed of semiconductor material.