Patents by Inventor Kuo-Feng Huang

Kuo-Feng Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240243016
    Abstract: A semiconductor device includes a first transistor located in a first region of a substrate and a second transistor located in a second region of the substrate. The first transistor includes first channel members vertically stacked above the substrate and a first gate structure wrapping around each of the first channel members. The first gate structure includes a first interfacial layer. The second transistor includes second channel members vertically stacked above the substrate and a second gate structure wrapping around each of the second channel members. The second gate structure includes a second interfacial layer. The second interfacial layer has a first sub-layer and a second sub-layer over the first sub-layer. The first and second sub-layers include different material compositions. A total thickness of the first and second sub-layers is larger than a thickness of the first interfacial layer.
    Type: Application
    Filed: February 5, 2024
    Publication date: July 18, 2024
    Inventors: Chih-Wei Lee, Wen-Hung Huang, Kuo-Feng Yu, Jian-Hao Chen, Hsueh-Ju Chen, Zoe Chen
  • Publication number: 20240079524
    Abstract: A semiconductor device comprises a first semiconductor structure, a second semiconductor structure located on the first semiconductor structure, and an active layer located between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure has a first conductivity type, and includes a plurality of first layers and a plurality of second layers alternately stacked. The second semiconductor structure has a second conductivity type opposite to the first conductivity type. The plurality of first layers and the plurality of second layers include indium and phosphorus, and the plurality of first layers and the plurality of second layers respectively have a first indium atomic percentage and a second indium atomic percentage. The second indium atomic percentage is different from the first indium atomic percentage.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 7, 2024
    Inventors: Wei-Jen HSUEH, Shih-Chang LEE, Kuo-Feng HUANG, Wen-Luh LIAO, Jiong-Chaso SU, Yi-Chieh LIN, Hsuan-Le LIN
  • Patent number: 11908953
    Abstract: A manufacturing method of a memory device are provided. The method includes following steps. A gate stacking structure is formed over a substrate. A first insulating layer, a second insulating layer and a mask material layer are sequentially formed over the substrate to cover the gate stacking structure. An ion implantation process is performed on the mask material layer to form a doped portion in the mask material layer. The doped portion caps on a top portion of the gate stacking structure. A first patterning process is performed on the mask material layer using the doped portion as a shadow mask to remove a bottom portion of the mask material layer extending along a surface of the substrate. A second patterning process is performed to remove the doped portion of the mask material layer and an exposed bottom portion of the second insulating layer surrounding the gate stacking structure.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: February 20, 2024
    Assignee: Winbond Electronics Corp.
    Inventors: Che-Jui Hsu, Ying-Fu Tung, Chun-Sheng Lu, Kuo-Feng Huang, Yu-Chi Kuo, Wang-Ta Li
  • Publication number: 20230371275
    Abstract: A semiconductor device according to the present disclosure includes a first conductive feature and a second conductive feature in a first dielectric layer, a buffer layer over the first dielectric layer, a second dielectric layer over the buffer layer, a first bottom via extending through the buffer layer and the second dielectric layer, a second bottom via extending through the buffer layer and the second dielectric layer, a first bottom electrode disposed on the first bottom via, a second bottom electrode disposed on the second bottom via, a first magnetic tunnel junction (MTJ) stack over the first bottom electrode, and a second MTJ stack over the second bottom electrode. The first MTJ stack and the second MTJ stack have a same thickness. The first MTJ stack has a first width and the second MTJ stack has a second width greater than the first width.
    Type: Application
    Filed: August 3, 2022
    Publication date: November 16, 2023
    Inventors: Yu-Jen Wang, Sheng-Huang Huang, Harry-Hak-Lay Chuang, Hung Cho Wang, Ching-Huang Wang, Kuo-Feng Huang
  • Publication number: 20230121256
    Abstract: A manufacturing method of a memory device are provided. The method includes following steps. A gate stacking structure is formed over a substrate. A first insulating layer, a second insulating layer and a mask material layer are sequentially formed over the substrate to cover the gate stacking structure. An ion implantation process is performed on the mask material layer to form a doped portion in the mask material layer. The doped portion caps on a top portion of the gate stacking structure. A first patterning process is performed on the mask material layer using the doped portion as a shadow mask to remove a bottom portion of the mask material layer extending along a surface of the substrate. A second patterning process is performed to remove the doped portion of the mask material layer and an exposed bottom portion of the second insulating layer surrounding the gate stacking structure.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 20, 2023
    Applicant: Winbond Electronics Corp.
    Inventors: Che-Jui Hsu, Ying-Fu Tung, Chun-Sheng Lu, Kuo-Feng Huang, Yu-Chi Kuo, Wang-Ta Li
  • Patent number: 11588072
    Abstract: A semiconductor device is provided, which includes a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first dopant. The second semiconductor structure is located on the first semiconductor structure and includes a second dopant different from the first dopant. The active region includes a plurality of semiconductor pairs and is located between the first semiconductor structure and the second semiconductor structure. One of the plurality of semiconductor pairs has a barrier layer and a well layer and includes the first dopant. The barrier layer has a first thickness and a first Al content, and the well layer has a second thickness and a second Al content, the second thickness is less than the first thickness, and the second Al content is less than the first Al content.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: February 21, 2023
    Assignee: EPISTAR CORPORATION
    Inventors: Yen-Chun Tseng, Kuo-Feng Huang, Shih-Chang Lee, Ming-Ta Chin, Shih-Nan Yen, Cheng-Hsing Chiang, Chia-Hung Lin, Cheng-Long Yeh, Yi-Ching Lee, Jui-Che Sung, Shih-Hao Cheng
  • Patent number: 11575051
    Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a gate stacking structure, a first insulating layer, a second insulating layer and a first spacer. The gate stacking structure is disposed over a substrate. The first insulating layer covers a top surface and a sidewall of the gate stacking structure. The second insulating layer covers a surface of the first insulating layer. A top corner region of the gate stacking structure is covered by the first and second insulating layers. The first spacer is located on the sidewall of the gate stacking structure, and covers a surface of the second insulating layer. A topmost end of the first spacer is lower than a topmost surface of the second insulating layer.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: February 7, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Che-Jui Hsu, Ying-Fu Tung, Chun-Sheng Lu, Kuo-Feng Huang, Yu-Chi Kuo, Wang-Ta Li
  • Publication number: 20220291306
    Abstract: Disclosed methods include placing a semiconductor wafer containing MRAM devices into a first magnetic field that has a magnitude sufficient to magnetically polarize MRAM bits and has a substantially uniform field strength and direction over the entire area of the wafer. The method further includes placing the wafer in a second magnetic field having an opposite field direction, a substantially uniform field strength and direction over the entire area of the wafer, and magnitude less than a design threshold for MRAM bit magnetization reversal. The method further includes determining a presence of malfunctioning MRAM bits by determining that such malfunctioning MRAM bits have a magnetic polarization that was reversed due to exposure to the second magnetic field. Malfunctioning MRAM bits may further be characterized by electrically reading data bits, or by using a chip probe to read one or more of voltage, current, resistances, etc., of the MRAM devices.
    Type: Application
    Filed: September 9, 2021
    Publication date: September 15, 2022
    Inventors: Cheng-Wei Chien, Harry-Hak-Lay Chuang, Kuei-Hung Shen, Kuo-Feng Huang, Bo-Hung Lin, Chun-Chi Chen
  • Publication number: 20210135052
    Abstract: A semiconductor device is provided, which includes a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first dopant. The second semiconductor structure is located on the first semiconductor structure and includes a second dopant different from the first dopant. The active region includes a plurality of semiconductor pairs and is located between the first semiconductor structure and the second semiconductor structure. One of the plurality of semiconductor pairs has a barrier layer and a well layer and includes the first dopant. The barrier layer has a first thickness and a first Al content, and the well layer has a second thickness and a second Al content, the second thickness is less than the first thickness, and the second Al content is less than the first Al content.
    Type: Application
    Filed: November 4, 2020
    Publication date: May 6, 2021
    Inventors: Yen-Chun Tseng, Kuo-Feng Huang, Shih-Chang Lee, Ming-Ta Chin, Shih-Nan Yen, Cheng-Hsing Chiang, Chia-Hung Lin, Cheng-Long Yeh, Yi-Ching Lee, Jui-Che Sung, Shih-Hao Cheng
  • Patent number: 10958093
    Abstract: The present disclosure relates to a power management system. The power management system comprises a first power supply device, a second power supply device, a power supply control device, a data processing device and a load. The power supply control device is connected to the first power supply device. The data processing device is connected to the first power supply device, the second power supply device and the power supply control device. The load is connected to the first power supply device and the second power supply device. The power supply control device is configured to, when activated, provide a first signal to the data processing device. The data processing device is configured to select the first power supply device or the second power supply device to provide power to the load according to the first signal.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: March 23, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tau-Jing Yang, Kuo-Feng Huang, Chih Lung Hung
  • Publication number: 20210066493
    Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a gate stacking structure, a first insulating layer, a second insulating layer and a first spacer. The gate stacking structure is disposed over a substrate. The first insulating layer covers a top surface and a sidewall of the gate stacking structure. The second insulating layer covers a surface of the first insulating layer. A top corner region of the gate stacking structure is covered by the first and second insulating layers. The first spacer is located on the sidewall of the gate stacking structure, and covers a surface of the second insulating layer. A topmost end of the first spacer is lower than a topmost surface of the second insulating layer.
    Type: Application
    Filed: August 20, 2020
    Publication date: March 4, 2021
    Applicant: Winbond Electronics Corp.
    Inventors: Che-Jui Hsu, Ying-Fu Tung, Chun-Sheng Lu, Kuo-Feng Huang, Yu-Chi Kuo, Wang-Ta Li
  • Patent number: 10916473
    Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: February 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hao Chung, Chang-Sheng Lin, Kuo-Feng Huang, Li-Chieh Wu, Chun-Chieh Lin
  • Patent number: 10811564
    Abstract: A light-emitting device is provided. The light-emitting device comprises The light-emitting device comprises a light-emitting stack comprising a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer; and a third semiconductor layer on the light-emitting stack and comprising a first sub-layer, a second sub-layer and a roughened surface, wherein the first sub-layer has the same composition as that of the second sub-layer, and the second sub-layer is farther from the light-emitting stack than the first sub-layer; wherein the first sub-layer and the second sub-layer each comprises a Group III element and a Group V element, and an atomic ratio of the Group III element to the Group V element of the first sub-layer is less than an atomic ratio of the Group III element to the Group V element of the second sub-layer.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: October 20, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Kuo-Feng Huang, Cheng-Hsing Chiang, Jih-Ming Tu
  • Patent number: 10749077
    Abstract: An optoelectronic device includes a semiconductor stack including a first surface and a second surface opposite to the first surface; a first contact layer on the first surface; and a second contact layer on the second surface. The second contact layer is not overlapped with the first contact layer in a vertical direction. The second contact layer includes a plurality of dots separating to each other and formed of semiconductor material.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: August 18, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chun-Yu Lin, Yung-Fu Chang, Rong-Ren Lee, Kuo-Feng Huang, Cheng-Long Yeh, Yi-Ching Lee, Ming-Siang Huang, Ming-Tzung Liou
  • Patent number: 10741381
    Abstract: A cleaning apparatus and a method of using the cleaning apparatus are provided. The method includes first moving a pencil pad into contact with a top surface of a wafer, wherein the pencil pad is connected to a pivot arm and second moving the pivot arm in a sweeping motion from a first zone to a second zone, the first zone being closer to a center of the top surface of the wafer than the second zone, wherein the sweeping motion is controlled by a controller, the pivot arm moves at a first speed in the first zone and the pivot arm moves at a second speed in the second zone, wherein the first speed is different from the second speed.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kaw-Wei Kuo, Chun-Hao Kung, Kuo-Feng Huang, Yi-Wei Chiu, Wei-Chun Chen
  • Patent number: 10741721
    Abstract: A light-emitting device is provided. The light-emitting device comprises a substrate; an insulating layer on the substrate, wherein the insulating layer comprises a first hole; a light-emitting stack on the insulating layer and comprising an active region comprising a top surface, wherein the top surface comprises a first part and a second part; and an opaque layer covering the first part of the top surface and exposing the second part of the top surface, wherein the second part is directly above the first hole.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: August 11, 2020
    Assignee: EPISTAR Corporation
    Inventors: Cheng-Feng Yu, Ching-Yuan Tsai, Yao-Ru Chang, Hsin-Chan Chung, Shih-Chang Lee, Wen-Luh Liao, Cheng-Hsing Chiang, Kuo-Feng Huang, Hsu-Hsuan Teng, Hung-Ta Cheng, Yung-Fu Chang
  • Publication number: 20200220372
    Abstract: The present disclosure relates to a power management system. The power management system comprises a first power supply device, a second power supply device, a power supply control device, a data processing device and a load. The power supply control device is connected to the first power supply device. The data processing device is connected to the first power supply device, the second power supply device and the power supply control device. The load is connected to the first power supply device and the second power supply device. The power supply control device is configured to, when activated, provide a first signal to the data processing device. The data processing device is configured to select the first power supply device or the second power supply device to provide power to the load according to the first signal.
    Type: Application
    Filed: March 18, 2020
    Publication date: July 9, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tau-Jing YANG, Kuo-Feng HUANG, Chih Lung HUNG
  • Patent number: 10622836
    Abstract: The present disclosure relates to a power management system. The power management system comprises a first power supply device, a second power supply device, a power supply control device, a data processing device and a load. The power supply control device is connected to the first power supply device. The data processing device is connected to the first power supply device, the second power supply device and the power supply control device. The load is connected to the first power supply device and the second power supply device. The power supply control device is configured to, when activated, provide a first signal to the data processing device. The data processing device is configured to select the first power supply device or the second power supply device to provide power to the load according to the first signal.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: April 14, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tau-Jing Yang, Kuo-Feng Huang, Chih Lung Hung
  • Patent number: 10580937
    Abstract: An optoelectronic device includes a semiconductor structure having a first side and a second side opposite to the first side, a first pad at the first side, a first finger connected to the electrode pad and having a first width, an insulating layer at the second side and comprising a first part under the first finger, the first part having a bottom surface with a second width larger than the first width and a side surface inclined to the bottom surface, and a contact layer covering the bottom surface and the side surface.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 3, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chun-Yu Lin, Yung-Fu Chang, Rong-Ren Lee, Kuo-Feng Huang, Cheng-Long Yeh, Yi-Ching Lee, Ming-Siang Huang, Ming-Tzung Liou
  • Patent number: D950421
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: May 3, 2022
    Assignee: KWANG YANG MOTOR CO., LTD.
    Inventors: Kuo-Feng Huang, Ping-Huan Chuang, Ming-Yi Shen, Bo-Jin Wang