Patents by Inventor Kuo-Tai Huang

Kuo-Tai Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190148226
    Abstract: An integrated circuit (IC) device includes a substrate having a fin-type active region extending in a first direction, a gate structure intersecting the fin-type active region on the substrate, the gate structure extending in a second direction perpendicular to the first direction and parallel to a top surface of the substrate, source and drain regions on both sides of the gate structure, and a first contact structure electrically connected to one of the source and drain regions, the first contact structure including a first contact plug including a first material and a first wetting layer surrounding the first contact plug, the first wetting layer including a second material having a lattice constant that differs from a lattice constant of the first material by about 10% or less.
    Type: Application
    Filed: October 9, 2018
    Publication date: May 16, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jeong-hyuk YIM, Kuo Tai HUANG, Wan-don KIM, Sang-jin HYUN
  • Publication number: 20190115451
    Abstract: Methods of fabricating a semiconductor device are provided. The methods may include forming an active pattern on a substrate, forming a gate electrode traversing the active pattern on the active pattern, forming a recess adjacent to a sidewall of the gate electrode in the active pattern, and performing a chemical vapor deposition process using a source gas and a doping gas to form a source/drain region in the recess. The source gas may include a silicon precursor and a germanium precursor, and the doping gas may include a gallium precursor and a boron precursor.
    Type: Application
    Filed: August 1, 2018
    Publication date: April 18, 2019
    Inventors: Joon Gon Lee, Kuo Tai Huang, Ryuji Tomita
  • Publication number: 20180247937
    Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure in the semiconductor substrate for isolating a first active region and a second active region, a first device formed in the first active region, and a second device formed in the second active region. The first device has a first gate dielectric layer and a first gate electrode over the first gate dielectric layer. The first gate electrode includes at least one of Ta and C, and has a first work function for a first conductivity. The second device has a second gate dielectric layer and a second gate electrode over the second gate dielectric layer. The second gate electrode includes at least one of Ta, C, and Al, and has a second work function for a second conductivity. The second conductivity is different from the first conductivity.
    Type: Application
    Filed: April 25, 2018
    Publication date: August 30, 2018
    Inventors: Yih-Ann Lin, Ryan Chia-Jen Chen, Donald Y. Chao, Yi-Shien Mor, Kuo-Tai Huang
  • Patent number: 9960160
    Abstract: The present disclosure describes a semiconductor device. The device includes a semiconductor substrate, an isolation structure formed in the substrate for isolating a first active region and a second active region, a first transistor formed in the first active region, the first transistor having a high-k gate dielectric layer and a metal gate with a first work function formed over the high-k gate dielectric layer, and a second transistor formed in the second active region, the second transistor having the high-k gate dielectric layer and a metal gate with a second work function formed over the high-k gate dielectric layer. The metal gates are formed from at least a single metal layer having the first work function and the second work function.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yih-Ann Lin, Ryan Chia-Jen Chen, Donald Y. Chao, Yi-Shien Mor, Kuo-Tai Huang
  • Patent number: 9728465
    Abstract: In a method of manufacturing a semiconductor device, a first gate structure and a second gate structure are formed on a substrate in a first region and a second region, respectively. A first semiconductor pattern including germanium is formed in the first region on the substrate. A first metal layer is formed on the substrate to cover the first semiconductor pattern. A first heat treatment process is performed such that the first semiconductor pattern and the first metal layer react with each other to form a first metal-semiconductor composite pattern in the first region and a semiconductor material of the substrate and the first metal layer react with each other to form a second metal-semiconductor composite pattern in the second region. The first metal-semiconductor composite pattern is removed from the substrate. A second metal layer is formed on the substrate to cover the second metal-semiconductor composite pattern. The second metal layer includes a material different from the first metal layer.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: August 8, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joon-Gon Lee, Ryuji Tomita, Sang-Jin Hyun, Kuo Tai Huang
  • Patent number: 9601388
    Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a first dielectric layer over the semiconductor substrate, forming a first metal layer over the first dielectric layer, the first metal layer having a first work function, removing at least a portion of the first metal layer in the second region, and thereafter, forming a semiconductor layer over the first metal layer in the first region and over the at least partially removed first metal layer in the second region. The method further includes removing the semiconductor layer and forming a second metal layer on the first metal layer in the first region and on the at least partially removed first metal layer in the second region, the second metal layer having a second work function that is different than the first work function.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ryan Chia-Jen Chen, Jr-Jung Lin, Chien-Hao Chen, Yi-Hsing Chen, Kuo-Tai Huang, Yih-Ann Lin, Yi-Shien Mor
  • Patent number: 9564488
    Abstract: A method of forming an isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: February 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mong-Song Liang, Tze-Liang Lee, Kuo-Tai Huang, Chao-Cheng Chen, Hao-Ming Lien, Chih-Tang Peng
  • Publication number: 20160293490
    Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a first dielectric layer over the semiconductor substrate, forming a first metal layer over the first dielectric layer, the first metal layer having a first work function, removing at least a portion of the first metal layer in the second region, and thereafter, forming a semiconductor layer over the first metal layer in the first region and over the at least partially removed first metal layer in the second region. The method further includes removing the semiconductor layer and forming a second metal layer on the first metal layer in the first region and on the at least partially removed first metal layer in the second region, the second metal layer having a second work function that is different than the first work function.
    Type: Application
    Filed: January 29, 2016
    Publication date: October 6, 2016
    Inventors: Ryan Chia-Jen Chen, Jr-Jung Lin, Chien-Hao Chen, Yi-Hsing Chen, Kuo-Tai Huang, Yih-Ann Lin, Yi-Shien Mor
  • Publication number: 20160133525
    Abstract: In a method of manufacturing a semiconductor device, a first gate structure and a second gate structure are formed on a substrate in a first region and a second region, respectively. A first semiconductor pattern including germanium is formed in the first region on the substrate. A first metal layer is formed on the substrate to cover the first semiconductor pattern. A first heat treatment process is performed such that the first semiconductor pattern and the first metal layer react with each other to form a first metal-semiconductor composite pattern in the first region and a semiconductor material of the substrate and the first metal layer react with each other to form a second metal-semiconductor composite pattern in the second region. The first metal-semiconductor composite pattern is removed from the substrate. A second metal layer is formed on the substrate to cover the second metal-semiconductor composite pattern. The second metal layer includes a material different from the first metal layer.
    Type: Application
    Filed: October 2, 2015
    Publication date: May 12, 2016
    Inventors: Joon-Gon LEE, Ryuji TOMITA, Sang-Jin HYUN, Kuo Tai HUANG
  • Patent number: 9263445
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Fu Hsu, Kang-Cheng Lin, Kuo-Tai Huang
  • Patent number: 9257426
    Abstract: A semiconductor device includes a semiconductor substrate that has a first-type active region and a second-type active region, a dielectric layer over the semiconductor substrate, a first metal layer having a first work function formed over the dielectric layer, the first metal layer being at least partially removed from over the second-type active region, a second metal layer over the first metal layer in the first-type active region and over the dielectric layer in the second-type active region, the second metal layer having a second work function, and a third metal layer over the second metal layer in the first-type active region and over the second metal layer in the second-type active region.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ryan Chia-Jen Chen, Yi-Shien Mor, Yi-Hsing Chen, Kuo-Tai Huang, Chien-Hao Chen, Yih-Ann Lin, Jr Jung Lin
  • Publication number: 20150061031
    Abstract: A semiconductor device includes a semiconductor substrate that has a first-type active region and a second-type active region, a dielectric layer over the semiconductor substrate, a first metal layer having a first work function formed over the dielectric layer, the first metal layer being at least partially removed from over the second-type active region, a second metal layer over the first metal layer in the first-type active region and over the dielectric layer in the second-type active region, the second metal layer having a second work function, and a third metal layer over the second metal layer in the first-type active region and over the second metal layer in the second-type active region.
    Type: Application
    Filed: September 10, 2014
    Publication date: March 5, 2015
    Inventors: Ray Chia-Jen Chen, Yi-Shien Mor, Yi-Hsing Chen, Kuo-Tai Huang, Chien-Hao Chen, Yih-Ann Lin, Jr Jung Lin
  • Publication number: 20150021705
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.
    Type: Application
    Filed: October 6, 2014
    Publication date: January 22, 2015
    Inventors: Peng-Fu Hsu, Kang-Cheng Lin, Kuo-Tai Huang
  • Patent number: 8853068
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Fu Hsu, Kang-Cheng Lin, Kuo-Tai Huang
  • Patent number: 8841731
    Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: September 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Jr Jung Lin, Yi-Shien Mor, Chien-Hao Chen, Kuo-Tai Huang, Yi-Hsing Chen
  • Patent number: 8836038
    Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yong-Tian Hou, Peng-Fu Hsu, Jin Ying, Kang-Cheng Lin, Kuo-Tai Huang, Tze-Liang Lee
  • Publication number: 20140242776
    Abstract: A method of forming an isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.
    Type: Application
    Filed: April 22, 2014
    Publication date: August 28, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mong-Song Liang, Tze-Liang Lee, Kuo-Tai Huang, Chao-Cheng Chen, Hao-Ming Lien, Chih-Tang Peng
  • Patent number: 8736016
    Abstract: An isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mong-Song Liang, Tze-Liang Lee, Kuo-Tai Huang, Chao-Cheng Chen, Hao-Ming Lien, Chih-Tang Peng
  • Publication number: 20140001566
    Abstract: The present disclosure describes a semiconductor device. The device includes a semiconductor substrate, an isolation structure formed in the substrate for isolating a first active region and a second active region, a first transistor formed in the first active region, the first transistor having a high-k gate dielectric layer and a metal gate with a first work function formed over the high-k gate dielectric layer, and a second transistor formed in the second active region, the second transistor having the high-k gate dielectric layer and a metal gate with a second work function formed over the high-k gate dielectric layer. The metal gates are formed from at least a single metal layer having the first work function and the second work function.
    Type: Application
    Filed: August 29, 2013
    Publication date: January 2, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yih-Ann Lin, Ryan Chia-Jen Chen, Yuan-Shun Chao, Yi-Shien Mor, Kuo-Tai Huang
  • Patent number: 8551837
    Abstract: Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: October 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yih-Ann Lin, Ryan Chia-Jen Chen, Chien-Hao Chen, Kuo-Tai Huang, Yi-Hsing Chen, Jr Jung Lin, Yu Chao Lin