Abstract: A N2O in-situ steam generation (N2O-ISSG) process for forming an ultra-thin nitrided oxide layer is provided. The N2O-ISSG process includes placing a silicon substrate in a process chamber, and then introducing a gas mixture comprising N2O and H2 into the process chamber at a pressure lower than 10 torr. Thereafter, heating the surface of the silicon substrate to a predetermined temperature about 800˜1100° C. to cause growth of a nitrided silicon dioxide layer on the heated surface of the silicon substrate. The nitrided silicon dioxide layer has nitrogen with a content about 1˜5 atomic %.

Abstract: This invention relates to a method that prevents by-productions from moving from a spacer. In particular by using an offset liner, a liner with a treated surface and a spacer that is formed by using the atomic layer deposition method or the rapid thermal chemical vapor deposition method. The present invention uses a liner, whose surface is treated, and a spacer, which is formed by using the atomic layer deposition method or the rapid thermal chemical vapor deposition method. This prevents by-product ions from moving from the spacer to other regions by using actions in diffusion and drift to affect the voltage stability of the semiconductor device after the current is connected. This defect will further affect qualities of the semiconductor device.

Abstract: A method of fabricating a DRAM capacitor uses tungsten nitride in the process of forming a capacitor. The structure of the capacitor is simple and the process is easily executed. Furthermore, the invention provides a method of forming tungsten nitride, comprising a step of implanting nitrogen into a tungsten silicide layer and a step of executing a rapid thermal process under ammonia gas to form a tungsten nitride layer on the surface of the tungsten silicide layer. The method of fabricating a DRAM capacitor comprises forming the tungsten silicide layer after forming a part smaller than a bottom electrode of the capacitor from doped polysilicon and forming tungsten nitride on the surface of the tungsten nitride layer.

Abstract: A method for manufacturing the lower electrode of a DRAM capacitor. The method includes depositing polysilicon instead of amorphous silicon to form the lower electrode. Because polysilicon has a higher depositing temperature, it has a higher depositing rate capable of shortening depositing time. After forming the polysilicon lower electrode, the upper portion of the polysilicon layer is transformed into an amorphous layer by bombarding the polysilicon layer with ions to damage its internal structure. Eventually, hemispherical grain silicon is able to grow over the lower electrode, thereby increasing its surface area.

Abstract: A method of fabricating a dual metal gate. A cell region and a peripheral region are formed on a substrate, and a first dummy gate electrode and a second dummy gate electrode are formed on the substrate, respectively, in the cell region and in the peripheral region. A patterned first dielectric layer is formed above the substrate, and the layer exposes the surfaces of the first dummy gate electrode and the second dummy gate electrode. The first dummy gate electrode and the second dummy gate electrode are then removed to expose the substrate, and an oxide layer is formed on the exposed substrate in the peripheral region. A remote plasma nitridation step is performed to nitridate the surface of the exposed substrate in the cell region and to nitridate the oxide layer into a material layer in the peripheral region. A second dielectric layer and a conducting layer are formed sequentially above the substrate.

Abstract: A method for forming a shallow trench isolation structure provides a substrate and a pad oxide layer is formed on the substrate to protect the substrate. A silicon nitride layer as a hard mask layer is deposited on the pad oxide layer, a shallow trench is defined by photolithography and etching. A liner oxide layer is formed on the surface of the shallow trench by thermal oxidation and a stress buffer layer is deposited conformal to the substrate by chemical vapor deposition. The stress buffer layer is used to release the stress and eliminate dislocations in the invention.

Abstract: A semiconductor fabrication method is provided for the fabrication of a dielectric structure for a storage capacitor in dynamic random-access memory (DRAM). In particular, the resultant dielectric structure can be fabricated thinner and more structurally-undefective than the prior art. By the method, a first nitridation process is performed to form a dielectric layer over a bottom electrode. Next, a layer of silicon nitride is formed over the dielectric layer. This silicon nitride layer would be typically formed with an undesired rugged surface with many punctures. To eliminate this structural defect, a second nitridation process is performed on the silicon nitride layer. The resultant silicon nitride layer and the dielectric layer in combination constitute an ON structure serving as the intended dielectric structure. Alternatively, an oxide layer can be further formed over the silicon nitride layer to constitute an ONO structure serving as the intended dielectric structure.

Abstract: A method of fabricating a capacitor. An isolation layer is formed on a substrate. An ion implantation step is performed. The isolation layer is patterned to form an opening in the isolation layer. The opening exposes a portion of the substrate. A patterned conductive layer is formed on the isolation layer to fill the opening. A hemispherical grained silicon layer is performed on the conductive layer. In addition, the step order of the ion implantation step can be changed. The ion implantation can also be performed after the opening is formed.

Abstract: A method of manufacturing shallow trench isolation structures. The method includes the steps of depositing insulating material into the trench of a substrate to form an insulation layer. The substrate has a plurality of active regions, each occupying a different area and having different sizes. In addition, there is a silicon nitride layer on top of each active region. Thereafter, a photoresist layer is then deposited over the insulation layer. Next, a portion of the photoresist layer is etched back to expose a portion of the oxide layer so that the remaining photoresist material forms a cap layer over the recessed area of the insulation layer. Subsequently, using the photoresist cap layer as a mask, the insulation layer is etched to remove a portion of the exposed oxide layer, thereby forming trenches within the oxide layer. After that, the photoresist cap layer is removed.

Abstract: A method of manufacturing a contact pad. A substrate having a source/drain region formed therein is provided. A dielectric layer is formed over the substrate. An opening is formed in the dielectric layer and exposes the source/drain region. A selective epitaxial process is performed to form a contact pad in the opening, wherein a top of the contact pad extends onto a surface of the dielectric layer.

Abstract: A method for fabricating a shallow trench isolation. A pad oxide layer and a mask layer are formed over a substrate. The pad oxide layer, the mask layer, and the substrate are patterned to form a trench exposing a portion of the substrate. A liner oxide layer is formed on the substrate exposed by the trench. An isolation layer is formed over the substrate to cover the liner oxide layer. The isolation layer is conformal to the trench. An oxide layer is formed over the substrate to fill the trench. A portion of the oxide layer and the isolation layer is removed until the mask layer is exposed. The mask layer and the pad oxide layer are removed to form a shallow trench isolation.

Abstract: A method of manufacturing a bottom electrode of a capacitor. A first dielectric layer is formed on a substrate. A cap layer is formed on the first dielectric layer. A second dielectric layer is formed on the cap layer. A node contact hole is formed to penetrate through the second dielectric layer, the cap layer and the first dielectric layer. A liner layer is formed on a sidewall of the node contact hole. A restraining layer is formed on the second dielectric layer. A patterned conductive layer is formed on a portion of the restraining layer and fills the node contact hole. A selective hemispherical grained layer is formed on the patterned conductive layer.

Abstract: A method for fabricating a gate structure. The method involves providing a substrate, followed by forming a nitride region on a surface of the substrate. With a Tantalum (Ta)-based organic compound and a Titanium (Ti)-based organic compound serving as precursors, an organic metal chemical vapor deposition (OMCVD) is performed, so that a Ta2−xTixO5 dielectric layer is formed on the substrate. A barrier layer, a conducting layer, and an anti-reflection (AR) layer are then formed in sequence on the Ta2−xTixO5 dielectric layer. Subsequently, the AR layer, the conducting layer, the barrier layer, and the Ta2−xTixO5 dielectric layer are defined to form a gate structure on the substrate of the nitride region. The Ta-based organic compound in this case may include a Ta-alkoxide compound, whereas the Ti-based organic compound may include a Ti-alkoxide compound or a Ti-amide compound.

Abstract: A method of fabricating a DRAM capacitor uses tungsten nitride in the process of forming a capacitor. The structure of the capacitor is simple and the process is easily executed. Furthermore, the invention provides a method of forming tungsten nitride, comprising a step of implanting nitrogen into a tungsten silicide layer and a step of executing a rapid thermal process under ammonia gas to form a tungsten nitride layer on the surface of the tungsten silicide layer. The method of fabricating a DRAM capacitor comprises forming the tungsten silicide layer after forming a part smaller than a bottom electrode of the capacitor from doped polysilicon and forming tungsten nitride on the surface of the tungsten nitride layer.

Abstract: The present invention relates to a method for forming excellent conformity due to improved surface sensitivity. A substrate is providing on which a transistor is formed. Moreover, a blanket first dielectric layer is deposited over the substrate. Then, a first photoresist layer is formed over the dielectric layer, wherein the first photoresist layer is defined and etched to form a contact opening. Further, a first conductive layer is formed to fill the contact opening, and performing an etching process to remove the first conductive layer to form a node contact. Consequentially, a second conductive layer is deposited over the first dielectric layer and the node contact. A second photoresist layer is formed over the second conductive layer, wherein the second photoresist layer is defined and etched to form a storage node as an upper electrode of a capacitor. Next, a hemispherical silicon grain (HSG) is formed over and on a sidewall of the second conductive layer.

Abstract: A method of manufacturing a dielectric film for a capacitor in a DRAM. A native oxide layer is removed using a rapid ramp process at a pressure lower than 10−5 torr. A nitridation is performed to form a dielectric layer on the surface of a storage electrode. A silicon nitride layer is formed on the dielectric layer. The rapid ramp process is started at a temperature of about 450-550° C. The temperature is raised at a rate of about 80-120° C./minute. The rapid ramp process is stopped at about 700-850° C. The nitridation is performed using a source gas, such as ammonia at about 700-850° C. for a relatively long time of about 10-60 minutes. The dielectric layer includes silicon nitride or silicon-oxy-nitride. An oxide layer is further formed on the silicon nitride layer. The oxide layer is formed by, for example, a rapid thermal process.

Abstract: A method of reducing the leakage current of a dielectric layer of a capacitor. A substrate having a dielectric layer formed thereon is disposed into a furnace. A first annealing step is performed for nucleation. A second annealing step is performed to control the number of the nuclei. A third annealing step is performed for grain growth.

Abstract: A method for fabricating a capacitor in an integrated circuit, using tantalum oxide as the dielectric layer to obtain a higher capacitance. A barrier layer is formed between the polysilicon layer and the tantalum oxide layer to prevent the formation of a silicon oxide layer. Thus, that capacitance of the capacitor is not reduced by the additional thickness of the silicon oxide layer.

Abstract: A fabricating method of a capacitor includes two gates and a commonly used source/drain region formed on a substrate. Then, a process of sell align contact has been applied to make a pitted self align contact window (PSACW) to partly expose the commonly used source/drain region. Then an glue/barrier layer and a lower electrode of the capacitor are formed over the PSACW. Then a dielectric thin film with a material having high dielectric constant is formed over the lower electrode. Then, an upper electrode is formed over the dielectric thin film to complete a capacitor, which has a structure of metal insulator metal with a shape like the PSACW.

Abstract: A method of fabricating a dielectric layer for a dynamic random access memory capacitor is described in which a tantalum pentoxide layer is deposited on the polysilicon storage electrode, followed by a two-step treatment on the tantalum pentoxide layer. The first treatment step includes a remote oxygen plasma or an ultraviolet-ozone treatment, followed by a spike annealing second treatment step.