Abstract: A method for forming a copper bump for flip chip bonding having improved oxidation resistance and thermal stability including providing a copper column having a thickness of at least about 40 microns overlying a metallurgy including an uppermost copper metal layer and a lowermost titanium layer the lowermost titanium layer in contact with an exposed copper bonding pad portion surrounded by a passivation layer; and, selectively depositing at least one protective metal layer over the copper column according to an electrolytic deposition process.

Abstract: A wafer level, chip scale package suitable for a MEMS type device employs a solder bead between a protective cap and the chip substrate to hermetically seal active areas of the chip. Solder is electroplated onto a metallized layer on the cap through a photoresist mask that is subsequently removed to leave a solder bead patterned to completely surround the active chip areas. The cap is mounted on the chip substrate using a spacer to hold the cap and the substrate in spaced relationship while the cap is welded to the chip substrate using the solder bead. The spacer is subsequently removed, preferably during dicing of a wafer on which the chips are formed.

Abstract: A method for forming a copper bump for flip chip bonding having improved oxidation resistance and thermal stability including providing a copper column having a thickness of at least about 40 microns overlying a metallurgy including an uppermost copper metal layer and a lowermost titanium layer the lowermost titanium layer in contact with an exposed copper bonding pad portion surrounded by a passivation layer; and, selectively depositing at least one protective metal layer over the copper column according to an electrolytic deposition process.

Abstract: A method of forming a wafer level chip scale package including forming a trench through the semiconductor wafer at a location between two adjacent to chip portions and forming a backside under bump metallurgy connection to an under bump metallurgy on the front face of the semiconductor wafer for each chip portion.

Abstract: A preparation method for an integrated assembly of a microchannel and an element is disclosed. In the preparation method of this invention, an element is prepared between a substrate and a sacrificial layer. Two protection layers, which are resistant to etchant for said substrate and said sacrificial layer, are prepared to isolate said element from its ambient environment. Said sacrificial layer defines an area to be etched off such that a microchannel may be formed. A coating layer with etching windows is then prepared on said sacrificial layer and the assembly is etched in an etchant to etch off said sacrificial layer and an area of said substrate beneath said sacrificial layer. An integrated assembly of a closed microchannel and an element is then accomplished. In the invented method, no bonding process is necessary and the integrated assembly so prepared has a planarization surface. This invention also disclosed a microchannel-element assembly prepared under the method of this invention.