Abstract: The offset between a reference clock output signal and a target clock output signal are measured during a predetermined period. Based on the measurement, an offset signal is generated. The offset signal is integrated into an average offset signal value, wherein the period of integration is the predetermined phase measurement time. The target clock is adjusted based on the average offset signal value so that the offset signal magnitude value approaches a predetermined limit. The process is iterated until the clocks are aligned within a predetermined tolerance.

Abstract: The offset between a reference clock output signal and a target clock output signal are measured during a predetermined period. Based on the measurement, an offset signal is generated. The offset signal is integrated into an average offset signal value, wherein the period of integration is the predetermined phase measurement time. The target clock is adjusted based on the average offset signal value so that the offset signal magnitude value approaches a predetermined limit. The process is iterated until the clocks are aligned within a predetermined tolerance. A tristatable XOR device may be used to measure phase difference, a simple RC circuit may be used to integrate the measured phase difference offset signal into the average offset signal and a low resolution A/D converter to digitize the average offset signal, before feeding the average offset signal value to the target clock.

Abstract: A high capacity packet switch is implemented using an expansion module that divides an incoming packet cell into a plurality of segments and supplies the segments, based on their sequential order, to respective ones of a plurality of concentrator units contained in the expansion module. Each concentrator unit includes a plurality of concentrator logic units and one of those logic units accepts a segment for storage based on routing information contained in the packet cell. The stored segments forming a packet cell are thereafter unloaded and recombined in proper sequence for routing to a packet switch module, which then forwards the packet cell toward its destination.

Abstract: A link interface to a high-speed asynchronous multiplexed ATM telecommunication link includes a data segmenter for forming ATM cells out of data frames, and a data assembler and state memory for assembling data frames out of received multiplexed (interleaved)ATM cells. A novel architecture implemented in hardware, and characterized by absence of intermediate storage of data in the data segmenter and pipelined operation of the data assembler, allows the link interface to operate at hundreds of Megabits and Gigabits per second.

Abstract: A digital trunk interface utilizing the first protocol handler to signal the start of a packet and a second protocol handler responsive to the packet delayed to initiate the storage of the packet internally to the digital trunk interface. The digital trunk interface comprises a microprocessor and two universal synchronous asynchronous receiver transmitter (USART) circuits. One USART is directly connected to the incoming digital trunk and is utilized to inform the microprocessor when a packet is first received. The second USART receives the packet delayed by a predefined amount of time from the digital trunk. The microprocessor is responsive to the signal from the first USART that a packet has been received to perform the necessary administrative functions for receipt of the packet by the second USART.

Abstract: A communication method and digital multi-customer data interface for interconnecting a number of customer terminals to a main packet switching network of a local area data transport system that provides data communication services such as interactive video text service between data service vendors and customers. The digital multi-customer interface utilizes a main processor, control circuit, and multi-customer protocol controller to implement the protocol functions for the communication of packets and control information over individual serial transmission paths. The multi-customer protocol controller comprises a control processor and a formatter circuit for synchronously communicating packets for a plurality of customer terminals via customer line units and customer lines. The control circuit handles communication of all control and status information between the main processor and the customer line units.