Abstract: A multinodal system is one-way interconnected, two-way interconnected or, more generally, (n)-way interconnected, where (n) is an integer. In a one-way interconnected system, only one connection element couples any two nodes. Or, put another way, only one communication path exists between every node and every other node. A two-way interconnected system, on the other hand, has two connection elements coupling each pair of nodes. Likewise, an (n)-way interconnected system provides (n) independent connection paths between each pair. Such systems are characteristic in that the relationship between the number of independent buses (b), the number of nodes (v), the number of ports (r), and the degree of interconnectedness (n) can be expressed by the equation ##EQU1## Two-way and (n)-way interconnect arrays may be adapted for use in fault-tolerant communications.

Abstract: A fault-tolerant digital data processing system comprises a first input-output controller which communicates with at least one peripheral device over a peripheral device bus having first and second input/output buses, each carrying data, address, control, and timing signals from the input/output controller to the peripheral device. A device interface is coupled to the first and second input/output buses and to an associated peripheral device for transferring information between the buses and the associated peripheral device. In normal operation, the device interface applies duplicate information signals synchronously and simultaneously to the input/output buses for transfer to the input/output controller. The device interface also receives, in the absence of fault, duplicative information signal synchronously and simultaneously from the first and second input/output buses.

Abstract: A fault-tolerant digital data processing system comprises at least a first input/output controller communicating with at least one peripheral device over a peripheral device bus. The peripheral bus includes first and second input/output buses, each having means for carrying data, address, control, and timing signals. The input/output controller includes an element for applying duplicate information signals synchronously and simultaneously to the first and second input/output buses for transfer to the peripheral device. The input/output controller further includes a bus interface element for receiving, in the absence of fault, duplicative information signals synchronously and simultaneously from the first and second input/output buses.

Abstract: A fault-tolerant digital data processor includes a peripheral device controller for communicating with one or more peripheral devices over a peripheral device bus having first and second input/output buses, each carrying data, address, control, and timing information. Each peripheral device includes a device interface for transferring information signals between the associated peripheral device and the peripheral bus. The peripheral device controller includes a strobe element connected with the first and second input/output buses for transmitting thereon duplicative, synchronous and simultaneous strobe signals. These strobe signals define successive timing intervals for information transfers along the peripheral bus. Information transfers are normally effected by the transmission of duplicate information signals synchronously and simultaneously on the first and second input/output buses.

Abstract: A fault-tolerant digital data processing system comprises at least a first peripheral controller communicating with at least one peripheral device over a peripheral device bus having first and second input/output buses, each carrying data, address, control, and timing signals. The first peripheral controller includes a first device interface element for applying duplicate information signals synchronously and simultaneously to the first and second input/output buses for transfer to the peripheral device. The first device interface element also receives, in the absence of fault, duplicative information signals synchronously and simultaneously from the first and second input/output buses. A second peripheral controller is coupled to the peripheral device bus for receiving the first and second input signals identically with the first peripheral controller.

Abstract: A fault-tolerant digital data processing system comprises at least a first input/output controller communicating with at least one peripheral device over a peripheral device bus. The peripheral bus includes first and second input/output buses, each having means for carrying data, address, control, and timing signals. The input/output controller includes an element for applying duplicate information signals synchronously and simultaneously to the first and second input/output buses for transfer to the peripheral device. The input/output controller further includes a bus interface element for receiving, in the absence of fault, duplicative information signals synchronously and simultaneously from the first and second input/output buses.

Abstract: Computer timing apparatus enables two clock elements to produce a single stream of timing pulses, without interruption, when both elements are operating normally, and when one element fails. The apparatus incorporates a multi-stable stage and an output logic stage. The multi-stable stage detects state transitions in the input signals of each clock element and generates a corresponding clock-tracking signal which can disable the output of the corresponding clock from propagating through the output logic. The output logic stage logically combines each clock signal with its corresponding clock-tracking signal, and logically combines the resultant signal to produce a single stream of output signals responsive to a next transition produced by either of the two clock elements.

Abstract: A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit.

Abstract: A fualt-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit.

Abstract: A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit.