Patents by Inventor Kurtis LESCHKIES
Kurtis LESCHKIES has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240123551Abstract: An apparatus for hole drilling in a substrate is provided. The apparatus includes a laser system configured to apply a laser beam onto the substrate for removing material from a set of areas on the substrate by directing the laser beam onto predefined positions corresponding to the set of areas on the substrate in a sequence. The apparatus includes a ventilation system configured to produce a fluid flow along one or more sides of the substrate. The apparatus controls the laser beam such that the laser beam is sequentially positioned according to a first laser beam movement direction and a second laser beam movement direction.Type: ApplicationFiled: March 10, 2021Publication date: April 18, 2024Inventors: Jeffrey L. FRANKLIN, Valentina FURIN, Giorgio CELLERE, Steven VERHAVERBEKE, Kurtis LESCHKIES, Han-Wen CHEN, Park GIBACK
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Patent number: 11881447Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.Type: GrantFiled: April 12, 2021Date of Patent: January 23, 2024Assignee: Applied Materials, Inc.Inventors: Han-Wen Chen, Steven Verhaverbeke, Giback Park, Kyuil Cho, Kurtis Leschkies, Roman Gouk, Chintan Buch, Vincent Dicaprio, Bernhard Stonas, Jean Delmas
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Publication number: 20240021582Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.Type: ApplicationFiled: July 27, 2023Publication date: January 18, 2024Inventors: Kurtis LESCHKIES, Han-Wen CHEN, Steven VERHAVERBEKE, Giback PARK, Kyuil CHO, Jeffrey L. FRANKLIN, Wei-Sheng LEI
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Patent number: 11862546Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.Type: GrantFiled: November 27, 2019Date of Patent: January 2, 2024Assignee: Applied Materials, Inc.Inventors: Han-Wen Chen, Steven Verhaverbeke, Giback Park, Kyuil Cho, Kurtis Leschkies, Roman Gouk, Chintan Buch, Vincent Dicaprio
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Publication number: 20230282498Abstract: The present disclosure relates to systems and methods for fabricating semiconductor packages, and more particularly, for forming features in semiconductor packages by laser ablation. In one embodiment, the laser systems and methods described herein can be utilized to pattern a substrate to be utilized as a package frame for a semiconductor package having one or more interconnections formed therethrough and/or one or more semiconductor dies disposed therein. The laser systems described herein can produce tunable laser beams for forming features in a substrate or other package structure. Specifically, frequency, pulse width, pulse shape, and pulse energy of laser beams are tunable based on desired sizes of patterned features and on the material in which the patterned features are formed. The adjustability of the laser beams enables rapid and accurate formation of features in semiconductor substrates and packages with controlled depth and topography.Type: ApplicationFiled: May 9, 2023Publication date: September 7, 2023Inventors: Kurtis LESCHKIES, Jeffrey L. FRANKLIN, Wei-Sheng LEI, Steven VERHAVERBEKE, Jean DELMAS, Han-Wen CHEN, Giback PARK
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Patent number: 11742330Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.Type: GrantFiled: January 18, 2022Date of Patent: August 29, 2023Assignee: Applied Materials, Inc.Inventors: Kurtis Leschkies, Han-Wen Chen, Steven Verhaverbeke, Giback Park, Kyuil Cho, Jeffrey L. Franklin, Wei-Sheng Lei
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Patent number: 11705365Abstract: The present disclosure relates to micro-via structures for interconnects in advanced wafer level semiconductor packaging. The methods described herein enable the formation of high-quality, low-aspect-ratio micro-via structures with improved uniformity, thus facilitating thin and small-form-factor semiconductor devices having high I/O density with improved bandwidth and power.Type: GrantFiled: May 18, 2021Date of Patent: July 18, 2023Assignee: Applied Materials, Inc.Inventors: Wei-Sheng Lei, Kurtis Leschkies, Roman Gouk, Giback Park, Kyuil Cho, Tapash Chakraborty, Han-Wen Chen, Steven Verhaverbeke
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Patent number: 11694912Abstract: Embodiments of the disclosure relate to an apparatus and method for annealing one or more semiconductor substrates. In one embodiment, a processing chamber is disclosed. The processing chamber includes a chamber body enclosing an internal volume, a substrate support disposed in the internal volume and configured to support a substrate during processing, a gas panel configured to provide a processing fluid into the internal volume, and a temperature-controlled fluid circuit configured to maintain the processing fluid at a temperature above a condensation point of the processing fluid. The temperature-controlled fluid circuit includes a gas conduit fluidly coupled to a port on the chamber body at a first end and to the gas panel at a second end.Type: GrantFiled: May 25, 2021Date of Patent: July 4, 2023Assignee: Applied Materials, Inc.Inventors: Jean Delmas, Steven Verhaverbeke, Kurtis Leschkies
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Patent number: 11676832Abstract: The present disclosure relates to systems and methods for fabricating semiconductor packages, and more particularly, for forming features in semiconductor packages by laser ablation. In one embodiment, the laser systems and methods described herein can be utilized to pattern a substrate to be utilized as a package frame for a semiconductor package having one or more interconnections formed therethrough and/or one or more semiconductor dies disposed therein. The laser systems described herein can produce tunable laser beams for forming features in a substrate or other package structure. Specifically, frequency, pulse width, pulse shape, and pulse energy of laser beams are tunable based on desired sizes of patterned features and on the material in which the patterned features are formed. The adjustability of the laser beams enables rapid and accurate formation of features in semiconductor substrates and packages with controlled depth and topography.Type: GrantFiled: July 24, 2020Date of Patent: June 13, 2023Assignee: Applied Materials, Inc.Inventors: Kurtis Leschkies, Jeffrey L. Franklin, Wei-Sheng Lei, Steven Verhaverbeke, Jean Delmas, Han-Wen Chen, Giback Park
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Publication number: 20220375787Abstract: The present disclosure relates to micro-via structures for interconnects in advanced wafer level semiconductor packaging. The methods described herein enable the formation of high-quality, low-aspect-ratio micro-via structures with improved uniformity, thus facilitating thin and small-form-factor semiconductor devices having high I/O density with improved bandwidth and power.Type: ApplicationFiled: May 18, 2021Publication date: November 24, 2022Inventors: Wei-Sheng LEI, Kurtis LESCHKIES, Roman GOUK, Giback PARK, Kyuil CHO, Tapash CHAKRABORTY, Han-Wen CHEN, Steven VERHAVERBEKE
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Patent number: 11469113Abstract: Disclosed herein is an apparatus and method for annealing semiconductor substrates. In one example the method of annealing substrates in a processing chamber includes loading a plurality of substrates into an internal volume of the processing chamber. The method includes flowing a processing fluid through a gas conduit into the internal volume. The method further includes measuring a temperature of the gas conduit at one or more position utilizing one or more temperature sensors. The processing fluid in the gas conduit and the internal volume are maintained at a temperature above a condensation point of the processing fluid.Type: GrantFiled: April 7, 2020Date of Patent: October 11, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Jean Delmas, Steven Verhaverbeke, Kurtis Leschkies
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Patent number: 11462417Abstract: Disclosed herein is an apparatus and method for annealing semiconductor substrates. In one example a temperature-controlled fluid circuit includes a condenser configured to fluidly connect to an internal volume of a processing chamber. The processing chamber has a body, the internal volume is within the body. The condenser is configured to condense a processing fluid into liquid phase. A source conduit includes a first terminal end that couples to a first port on the body of the processing chamber. The source conduit includes a second terminal end. The first terminal end couples to a gas panel. The gas panel is configured to provide a processing fluid into the internal volume of the processing chamber. A gas conduit includes a first end. The first end couples to the condenser and a second end. The second end is configured to couple to a second port on the body of the processing chamber.Type: GrantFiled: April 15, 2020Date of Patent: October 4, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Jean Delmas, Steven Verhaverbeke, Kurtis Leschkies
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Patent number: 11400545Abstract: A method of fabricating a frame to enclose one or more semiconductor dies includes forming one or more features including one or more cavities and one or more through-vias in a substrate by a first laser ablation process, filling the one or more through-vias with a dielectric material, and forming a via-in-via in the dielectric material filled in each of the one or more through-vias by a second laser ablation process. The one or more cavities is configured to enclose one or more semiconductor dies therein. In the first laser ablation process, frequency, pulse width, and pulse energy of a first pulsed laser beam to irradiate the substrate are tuned based on a depth of the one or more features. In the second laser ablation process, frequency, pulse width, and pulse energy of a second pulsed laser beam to irradiate the dielectric material are tuned based on a depth of the via-in-via.Type: GrantFiled: May 11, 2020Date of Patent: August 2, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Kurtis Leschkies, Wei-Sheng Lei, Jeffrey L. Franklin, Jean Delmas, Han-Wen Chen, Giback Park, Steven Verhaverbeke
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Publication number: 20220139884Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.Type: ApplicationFiled: January 18, 2022Publication date: May 5, 2022Inventors: Kurtis LESCHKIES, Han-Wen CHEN, Steven VERHAVERBEKE, Giback PARK, Kyuil CHO, Jeffrey L. FRANKLIN, Wei-Sheng LEI
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Patent number: 11257790Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.Type: GrantFiled: March 10, 2020Date of Patent: February 22, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Kurtis Leschkies, Han-Wen Chen, Steven Verhaverbeke, Giback Park, Kyuil Cho, Jeffrey L. Franklin, Wei-Sheng Lei
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Publication number: 20220044936Abstract: In an embodiment, a method of forming a blind via in a substrate comprising a mask layer, a conductive layer, and a dielectric layer is provided. The method includes detecting the mask layer by a sensor, the mask layer providing a substrate surface; determining a property of the blind via, the property comprising one or more of a top diameter, a bottom diameter, a volume, or a taper angle; focusing a Gaussian laser beam, under laser process parameters, at the substrate surface to remove at least a portion of the mask layer; adjusting the laser process parameters based on the property; and focusing the laser beam, under the adjusted laser process parameters, to remove at least a portion of the dielectric layer within the volume to form the blind via. The mask layer can be pre-etched. Apparatus for forming a blind via in a substrate are also provided.Type: ApplicationFiled: October 22, 2021Publication date: February 10, 2022Inventors: Wei-Sheng LEI, Kurtis LESCHKIES, Roman GOUK, Steven VERHAVERBEKE, Visweswaren SIVARAMAKRISHNAN
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Publication number: 20220028709Abstract: The present disclosure relates to systems and methods for fabricating semiconductor packages, and more particularly, for forming features in semiconductor packages by laser ablation. In one embodiment, the laser systems and methods described herein can be utilized to pattern a substrate to be utilized as a package frame for a semiconductor package having one or more interconnections formed therethrough and/or one or more semiconductor dies disposed therein. The laser systems described herein can produce tunable laser beams for forming features in a substrate or other package structure. Specifically, frequency, pulse width, pulse shape, and pulse energy of laser beams are tunable based on desired sizes of patterned features and on the material in which the patterned features are formed. The adjustability of the laser beams enables rapid and accurate formation of features in semiconductor substrates and packages with controlled depth and topography.Type: ApplicationFiled: July 24, 2020Publication date: January 27, 2022Inventors: Kurtis LESCHKIES, Jeffrey L. FRANKLIN, Wei-Sheng LEI, Steven VERHAVERBEKE, Jean DELMAS, Han-Wen CHEN, Giback PARK
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Patent number: 11232951Abstract: In an embodiment is provided a method of forming a blind via in a substrate comprising a mask layer, a conductive layer, and a dielectric layer that includes conveying the substrate to a scanning chamber; determining one or more properties of the blind via, the one or more properties comprising a top diameter, a bottom diameter, a volume, or a taper angle of about 80° or more; focusing a laser beam at the substrate to remove at least a portion of the mask layer; adjusting the laser process parameters based on the one or more properties; and focusing the laser beam, under the adjusted laser process parameters, to remove at least a portion of the dielectric layer within the volume to form the blind via. In some embodiments, the mask layer can be pre-etched. In another embodiment is provided an apparatus for forming a blind via in a substrate.Type: GrantFiled: July 14, 2020Date of Patent: January 25, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Wei-Sheng Lei, Kurtis Leschkies, Roman Gouk, Steven Verhaverbeke, Visweswaren Sivaramakrishnan
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Publication number: 20220020590Abstract: In an embodiment is provided a method of forming a blind via in a substrate comprising a mask layer, a conductive layer, and a dielectric layer that includes conveying the substrate to a scanning chamber; determining one or more properties of the blind via, the one or more properties comprising a top diameter, a bottom diameter, a volume, or a taper angle of about 80° or more; focusing a laser beam at the substrate to remove at least a portion of the mask layer; adjusting the laser process parameters based on the one or more properties; and focusing the laser beam, under the adjusted laser process parameters, to remove at least a portion of the dielectric layer within the volume to form the blind via. In some embodiments, the mask layer can be pre-etched. In another embodiment is provided an apparatus for forming a blind via in a substrate.Type: ApplicationFiled: July 14, 2020Publication date: January 20, 2022Inventors: Wei-Sheng LEI, Kurtis LESCHKIES, Roman GOUK, Steven VERHAVERBEKE, Visweswaren SIVARAMAKRISHNAN
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Patent number: 11227797Abstract: Embodiments described herein relate to methods of seam-free gapfilling and seam healing that can be carried out using a chamber operable to maintain a supra-atmospheric pressure (e.g., a pressure greater than atmospheric pressure). One embodiment includes positioning a substrate having one or more features formed in a surface of the substrate in a process chamber and exposing the one or more features of the substrate to at least one precursor at a pressure of about 1 bar or greater. Another embodiment includes positioning a substrate having one or more features formed in a surface of the substrate in a process chamber. Each of the one or more features has seams of a material. The seams of the material are exposed to at least one precursor at a pressure of about 1 bar or greater.Type: GrantFiled: November 6, 2019Date of Patent: January 18, 2022Assignee: Applied Materials, Inc.Inventors: Shishi Jiang, Kurtis Leschkies, Pramit Manna, Abhijit Mallick