Patents by Inventor Kushagra Vaid
Kushagra Vaid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10664166Abstract: Systems, apparatus, and computer-implemented methods are provided for the hybridization of cache memory utilizing both magnetic and solid-state memory media. A solid-state cache controller apparatus can be coupled to a host computing system to maximize efficiency of the system in a manner that is transparent to the high-level applications using the system. The apparatus includes an associative memory component and a solid-state cache control component. Solid-state memory is configured to store data blocks of host read operations. If a host-read operation is requested, the controller communicates with a solid-state cache memory controller to determine whether a tag array data structure indicates a cached copy of the requested data block is available in solid-state memory.Type: GrantFiled: July 9, 2015Date of Patent: May 26, 2020Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Kushagra Vaid, Sompong Paul Olarig
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Patent number: 9779249Abstract: In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.Type: GrantFiled: October 13, 2016Date of Patent: October 3, 2017Assignee: Intel CorporationInventors: John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert J. Greiner, James A. Sutton, Kushagra Vaid, Willard M. Wiseman
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Publication number: 20170098085Abstract: In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.Type: ApplicationFiled: October 13, 2016Publication date: April 6, 2017Inventors: John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert J. Greiner, James A. Sutton, Kushagra Vaid, Willard M. Wiseman
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Patent number: 9507952Abstract: In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.Type: GrantFiled: November 11, 2015Date of Patent: November 29, 2016Assignee: Intel CorporationInventors: John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert J. Greiner, James A. Sutton, Kushagra Vaid, Willard M. Wiseman
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Publication number: 20160063261Abstract: In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.Type: ApplicationFiled: November 11, 2015Publication date: March 3, 2016Inventors: John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert J. Greiner, James A. Sutton, Kushagra Vaid, Willard M. Wiseman
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Patent number: 9213865Abstract: In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.Type: GrantFiled: October 3, 2014Date of Patent: December 15, 2015Assignee: Intel CorporationInventors: John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert J. Greiner, James A. Sutton, Kushagra Vaid, Willard M. Wiseman
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Publication number: 20150309729Abstract: Systems, apparatus, and computer-implemented methods are provided for the hybridization of cache memory utilizing both magnetic and solid-state memory media. A solid-state cache controller apparatus can be coupled to a host computing system to maximize efficiency of the system in a manner that is transparent to the high-level applications using the system. The apparatus includes an associative memory component and a solid-state cache control component. Solid-state memory is configured to store data blocks of host read operations. If a host-read operation is requested, the controller communicates with a solid-state cache memory controller to determine whether a tag array data structure indicates a cached copy of the requested data block is available in solid-state memory.Type: ApplicationFiled: July 9, 2015Publication date: October 29, 2015Inventors: Kushagra Vaid, Sompong Paul Olarig
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Patent number: 9110783Abstract: Systems, apparatus, and computer-implemented methods are provided for the hybridization of cache memory utilizing both magnetic and solid-state memory media. A solid-state cache controller apparatus can be coupled to a host computing system to maximize efficiency of the system in a manner that is transparent to the high-level applications using the system. The apparatus includes an associative memory component and a solid-state cache control component. Solid-state memory is configured to store data blocks of host read operations. If a host-read operation is requested, the controller communicates with a solid-state cache memory controller to determine whether a tag array data structure indicates a cached copy of the requested data block is available in solid-state memory.Type: GrantFiled: September 14, 2012Date of Patent: August 18, 2015Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Kushagra Vaid, Sompong Paul Olarig
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Patent number: 8984265Abstract: In some embodiments, the invention involves a system and method relating to secure booting of a platform. In at least one embodiment, the present invention is intended to securely boot a platform using one or more signature keys stored in a secure location on the platform, where access to the signature is by a microcontroller on the platform and the host processor has no direct access to alter the signature key. Other embodiments are described and claimed.Type: GrantFiled: March 30, 2007Date of Patent: March 17, 2015Assignee: Intel CorporationInventors: Kushagra Vaid, Vincent J. Zimmer, Mrigank Shekhar
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Publication number: 20150059007Abstract: In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.Type: ApplicationFiled: October 3, 2014Publication date: February 26, 2015Inventors: John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert J. Greiner, James A. Sutton, Kushagra Vaid, Willard M. Wiseman
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Patent number: 8874906Abstract: In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.Type: GrantFiled: May 20, 2013Date of Patent: October 28, 2014Assignee: Intel CorporationInventors: John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert J. Greiner, James A. Sutton, Kushagra Vaid, Williard M. Wiseman
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Patent number: 8645959Abstract: A technique for performing barrier synchronization among a plurality of program threads. More particularly, at least one embodiment of the invention keeps track of completed tasks associated with a number of program threads using bits within a barrier register that can be updated and reassigned without incurring the amount of bus traffic as in the prior art.Type: GrantFiled: March 30, 2005Date of Patent: February 4, 2014Assignee: Intel CorporaitonInventors: Kushagra Vaid, John Crawford, Allen Baum
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Publication number: 20130254905Abstract: In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.Type: ApplicationFiled: May 20, 2013Publication date: September 26, 2013Inventors: John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert J. Greiner, James A. Sutton, Kushagra Vaid, Williard M. Wiseman
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Patent number: 8533514Abstract: The power draw of equipment in a data center may be capped in order to keep the power draw under the capacity of the Uninterruptable Power Supply (UPS) that serves the data center. The current capacity of the UPS may be estimated, and the equipment may be controlled so as to keep the equipment's power draw under that current capacity. Factors that may affect the estimate of the UPS's current capacity include the history of temperature and humidity to which the UPS has been subject, and charge/discharge history of the UPS. Factors that may affect the decision of which equipment to throttle to a lower power level include: the current power load at the data center, the type of software that each server is running, and the demand for that software.Type: GrantFiled: June 26, 2011Date of Patent: September 10, 2013Assignee: Microsoft CorporationInventors: Harry R. Rogers, Kushagra Vaid, Mark E. Shaw, Badriddine Khessib, Bryan Kelly, Matthew Faist
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Patent number: 8464048Abstract: In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.Type: GrantFiled: March 16, 2012Date of Patent: June 11, 2013Assignee: Intel CorporationInventors: John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert J. Greiner, James A. Sutton, Kushagra Vaid, Willard M. Wiseman
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Patent number: 8458412Abstract: The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.Type: GrantFiled: June 24, 2011Date of Patent: June 4, 2013Assignee: Intel CorporationInventors: Sailesh Kottapalli, John H. Crawford, Kushagra Vaid
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Publication number: 20120331317Abstract: The power draw of equipment in a data center may be capped in order to keep the power draw under the capacity of the Uninterruptable Power Supply (UPS) that serves the data center. The current capacity of the UPS may be estimated, and the equipment may be controlled so as to keep the equipment's power draw under that current capacity. Factors that may affect the estimate of the UPS's current capacity include the history of temperature and humidity to which the UPS has been subject, and charge/discharge history of the UPS. Factors that may affect the decision of which equipment to throttle to a lower power level include: the current power load at the data center, the type of software that each server is running, and the demand for that software.Type: ApplicationFiled: June 26, 2011Publication date: December 27, 2012Applicant: MICROSOFT CORPORATIONInventors: Harry R. Rogers, Kushagra Vaid, Mark E. Shaw, Badriddine Khessib, Bryan Kelly, Matthew Faist
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Patent number: 8321630Abstract: Systems, apparatus, and computer-implemented methods are provided for the hybridization of cache memory utilizing both magnetic and solid-state memory media. A solid-state cache controller apparatus can be coupled to a host computing system to maximize efficiency of the system in a manner that is transparent to the high-level applications using the system. The apparatus includes an associative memory component and a solid-state cache control component. Solid-state memory is configured to store data blocks of host read operations. If a host-read operation is requested, the controller communicates with a solid-state cache memory controller to determine whether a tag array data structure indicates a cached copy of the requested data block is available in solid-state memory.Type: GrantFiled: January 28, 2010Date of Patent: November 27, 2012Assignee: Microsoft CorporationInventors: Kushagra Vaid, Sompong Paul Olarig
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Publication number: 20120239906Abstract: In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.Type: ApplicationFiled: March 16, 2012Publication date: September 20, 2012Inventors: John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert J. Greiner, James A. Sutton, Kushagra Vaid, Willard M. Wiseman
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Patent number: 8250364Abstract: In one embodiment of the present invention, a method includes verifying an initiating logical processor of a system; validating a trusted agent with the initiating logical processor if the initiating logical processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.Type: GrantFiled: June 28, 2010Date of Patent: August 21, 2012Assignee: Intel CorporationInventors: John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert J. Greiner, James A. Sutton, Kushagra Vaid, Willard M. Wiseman