Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes an active pattern on a substrate, a device isolation layer provided on the substrate to define the active pattern, a pair of source/drain patterns on the active pattern and a channel pattern therebetween, the channel pattern including semiconductor patterns which are stacked and are spaced apart from each other, a gate electrode crossing the channel pattern, and a gate spacer on a side surface of the gate electrode. The gate spacer located on the device isolation layer includes an upper portion with a first thickness and a lower portion with a second thickness. The second thickness is larger than the first thickness, and the lower portion of the gate spacer is located at a level lower than the uppermost one of the semiconductor patterns.

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

Abstract: A semiconductor device includes a gate electrode extending in a first direction, on a substrate, first outer spacers extending along side surfaces of the gate electrode, a first active pattern extending in a second direction, which intersects the first direction, to penetrate the gate electrode and the first outer spacers, epitaxial patterns on the first active pattern and on side surfaces of the first outer spacers, second outer spacers between the first outer spacers and the epitaxial patterns and inner spacers between the substrate and the first active pattern and between the gate electrode and the epitaxial patterns, wherein in a cross section that intersects the second direction, at least parts of the second outer spacers are on side surfaces of the first active pattern and side surfaces of the inner spacers.

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

Abstract: A semiconductor device includes; an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern and including semiconductor patterns spaced apart in a vertical stack, and a gate electrode extending across the channel pattern. The semiconductor patterns includes a first semiconductor pattern and a second semiconductor pattern. The gate electrode includes a first part between the substrate and the first semiconductor pattern and a second part between the first semiconductor pattern and the second semiconductor pattern. A width of the first part varies with a depth of the first part, such that a width of a middle portion of the first part is less than a width of a lower portion of the first part and a width of an upper portion of the first part.

Abstract: A semiconductor device includes a gate electrode extending in a first direction, on a substrate, first outer spacers extending along side surfaces of the gate electrode, a first active pattern extending in a second direction, which intersects the first direction, to penetrate the gate electrode and the first outer spacers, epitaxial patterns on the first active pattern and on side surfaces of the first outer spacers, second outer spacers between the first outer spacers and the epitaxial patterns and inner spacers between the substrate and the first active pattern and between the gate electrode and the epitaxial patterns, wherein in a cross section that intersects the second direction, at least parts of the second outer spacers are on side surfaces of the first active pattern and side surfaces of the inner spacers.

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.

Abstract: Provided is a semiconductor device including: a fin structure on a substrate including a negative channel field-effect transistor (nFET) region and a positive channel field-effect transistor (pFET) region; a gate structure on the fin structure; and a source/drain structure adjacent to the gate structure, wherein the source/drain structure formed in the nFET region is an epitaxial layer including an n-type impurity at a concentration of about 1.8×1021/cm3 or more, includes silicon (Si) and germanium (Ge) on an outer portion of the source/drain structure, and includes Si but not Ge in an inner portion of the source/drain structure, wherein an inclined surface contacting an uppermost surface of the source/drain structure forms an angle of less than about 54.7° with a top surface of the fin structure.

Abstract: A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.

Abstract: Provided is a semiconductor device including: a fin structure on a substrate including a negative channel field-effect transistor (nFET) region and a positive channel field-effect transistor (pFET) region; a gate structure on the fin structure; and a source/drain structure adjacent to the gate structure, wherein the source/drain structure formed in the nFET region is an epitaxial layer including an n-type impurity at a concentration of about 1.8×1021/cm3 or more, includes silicon (Si) and germanium (Ge) on an outer portion of the source/drain structure, and includes Si but not Ge in an inner portion of the source/drain structure, wherein an inclined surface contacting an uppermost surface of the source/drain structure forms an angle of less than about 54.7° with a top surface of the fin structure.

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

Abstract: A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.

Abstract: A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.

Abstract: A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.

Abstract: Provided is a semiconductor device including: a fin structure on a substrate including a negative channel field-effect transistor (nFET) region and a positive channel field-effect transistor (pFET) region; a gate structure on the fin structure; and a source/drain structure adjacent to the gate structure, wherein the source/drain structure formed in the nFET region is an epitaxial layer including an n-type impurity at a concentration of about 1.8×1021/cm3 or more, includes silicon (Si) and germanium (Ge) on an outer portion of the source/drain structure, and includes Si but not Ge in an inner portion of the source/drain structure, wherein an inclined surface contacting an uppermost surface of the source/drain structure forms an angle of less than about 54.7° with a top surface of the fin structure.

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

Abstract: Provided is a semiconductor device including: a fin structure on a substrate including a negative channel field-effect transistor (nFET) region and a positive channel field-effect transistor (pFET) region; a gate structure on the fin structure; and a source/drain structure adjacent to the gate structure, wherein the source/drain structure formed in the nFET region is an epitaxial layer including an n-type impurity at a concentration of about 1.8×1021/cm3 or more, includes silicon (Si) and germanium (Ge) on an outer portion of the source/drain structure, and includes Si but not Ge in an inner portion of the source/drain structure, wherein an inclined surface contacting an uppermost surface of the source/drain structure forms an angle of less than about 54.7° with a top surface of the fin structure.

Abstract: A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.