Patents by Inventor Kwang Soo Ahn

Kwang Soo Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240107032
    Abstract: The present invention relates to an image encoding and decoding technique, and more particularly, to an image encoder and decoder using unidirectional prediction. The image encoder includes a dividing unit to divide a macro block into a plurality of sub-blocks, a unidirectional application determining unit to determine whether an identical prediction mode is applied to each of the plurality of sub-blocks, and a prediction mode determining unit to determine a prediction mode with respect to each of the plurality of sub-blocks based on a determined result of the unidirectional application determining unit.
    Type: Application
    Filed: December 7, 2023
    Publication date: March 28, 2024
    Applicants: Electronics and Telecommunications Research Institute, Kwangwoon University Industry-Academic Collaboration Foundation, University-Industry Cooperation Group of Kyung Hee University
    Inventors: Hae Chul CHOI, Se Yoon JEONG, Sung-Chang LIM, Jin Soo CHOI, Jin Woo HONG, Dong Gyu SIM, Seoung-Jun OH, Chang-Beom AHN, Gwang Hoon PARK, Seung Ryong KOOK, Sea-Nae PARK, Kwang-Su JEONG
  • Patent number: 10090058
    Abstract: A semiconductor device may be provided. The semiconductor device may be configured for detecting a defect of a fuse set. The semiconductor device may include a pseudo initial signal generator configured to generate pseudo initial information on the basis of a test mode signal. The semiconductor device may include a fuse-set defect detector configured to compare fuse-set information of a fuse set or the pseudo initial information with a reference value on the basis of a fuse-set address, and detect a defect of the fuse set.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: October 2, 2018
    Assignee: SK hynix Inc.
    Inventors: Sung Soo Chi, Dong Woo Lyu, Jin Yo Park, Sang Kyung Shin, Kwang Soo Ahn, Sung Su Cha
  • Publication number: 20180082754
    Abstract: A semiconductor device may be provided. The semiconductor device may be configured for detecting a defect of a fuse set. The semiconductor device may include a pseudo initial signal generator configured to generate pseudo initial information on the basis of a test mode signal. The semiconductor device may include a fuse-set defect detector configured to compare fuse-set information of a fuse set or the pseudo initial information with a reference value on the basis of a fuse-set address, and detect a defect of the fuse set.
    Type: Application
    Filed: March 6, 2017
    Publication date: March 22, 2018
    Applicant: SK hynix Inc.
    Inventors: Sung Soo CHI, Dong Woo LYU, Jin Yo PARK, Sang Kyung SHIN, Kwang Soo AHN, Sung Su CHA
  • Patent number: 9563549
    Abstract: Disclosed is an address mapping method for a data storage device using a hybrid mapping scheme. The address mapping method determines whether write data includes a defined super sequential block (SSB), and selects an address mapping mode for the write data in accordance with whether or not a SSB is present.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: February 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang Soo Ahn, Hyun Jin Choi
  • Publication number: 20120124276
    Abstract: Disclosed is an address mapping method for a data storage device using a hybrid mapping scheme. The address mapping method determines whether write data includes a defined super sequential block (SSB), and selects an address mapping mode for the write data in accordance with whether or not a SSB is present.
    Type: Application
    Filed: September 22, 2011
    Publication date: May 17, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang Soo Ahn, Hyun Jin Choi
  • Publication number: 20020089498
    Abstract: LCD driving circuit for applying a signal of a first polarity and a signal of a second polarity opposite to the first polarity to an LCD alternately, including first and second data latches for latching source data in succession, a DAC for converting a latch data into an analog signal to provide a signal of the first polarity, a driving signal processing block for receiving a converted signal from the DAC to provide a signal of the second polarity, a multiplexer for selecting either one of signals of first and second polarities in response to a polar signal, and a buffer for buffering a signal from the multiplexer and applying a source driving signal to LCD cells, thereby permitting to use only one type of DAC.
    Type: Application
    Filed: December 11, 2001
    Publication date: July 11, 2002
    Inventor: Kwang Soo Ahn