Patents by Inventor Kwang-Soo Seol

Kwang-Soo Seol has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12029040
    Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: July 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taekyung Kim, Kwang Soo Seol, Seong Soon Cho, Sunghoi Hur, Jintae Kang
  • Patent number: 11888042
    Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: January 30, 2024
    Inventors: Kwang Soo Seol, Chanjin Park, Kihyun Hwang, Hanmei Choi, Sunghoi Hur, Wansik Hwang, Toshiro Nakanishi, Kwangmin Park, Juyul Lee
  • Publication number: 20230127052
    Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.
    Type: Application
    Filed: December 16, 2022
    Publication date: April 27, 2023
    Inventors: TAEKYUNG KIM, KWANG SOO SEOL, SEONG SOON CHO, SUNGHOI HUR, JINTAE KANG
  • Patent number: 11588032
    Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: February 21, 2023
    Inventors: Kwang Soo Seol, Chanjin Park, Kihyun Hwang, Hanmei Choi, Sunghoi Hur, Wansik Hwang, Toshiro Nakanishi, Kwangmin Park, Juyul Lee
  • Publication number: 20230044895
    Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.
    Type: Application
    Filed: October 19, 2022
    Publication date: February 9, 2023
    Inventors: Kwang Soo Seol, Chanjin Park, Kihyun Hwang, Hanmei Choi, Sunghoi Hur, Wansik Hwang, Toshiro Nakanishi, Kwangmin Park, Juyul Lee
  • Patent number: 11545503
    Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: January 3, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taekyung Kim, Kwang Soo Seol, Seong Soon Cho, Sunghoi Hur, Jintae Kang
  • Publication number: 20210111260
    Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Inventors: Kwang Soo Seol, Chanjin Park, Kihyun Hwang, Hanmei Choi, Sunghoi Hur, Wansik Hwang, Toshiro Nakanishi, Kwangmin Park, Juyul Lee
  • Patent number: 10903327
    Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: January 26, 2021
    Inventors: Kwang Soo Seol, Chanjin Park, Kihyun Hwang, Hanmei Choi, Sunghoi Hur, Wansik Hwang, Toshiro Nakanishi, Kwangmin Park, Juyul Lee
  • Publication number: 20200258994
    Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Inventors: Kwang Soo Seol, Chanjin Park, Kihyun Hwang, Hanmei Choi, Sunghoi Hur, Wansik Hwang, Toshiro Nakanishi, Kwangmin Park, Juyul Lee
  • Publication number: 20200152643
    Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.
    Type: Application
    Filed: January 21, 2020
    Publication date: May 14, 2020
    Inventors: TAEKYUNG KIM, KWANG SOO SEOL, SEONG SOON CHO, SUNGHOI HUR, JINTAE KANG
  • Patent number: 10541248
    Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: January 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taekyung Kim, Kwang Soo Seol, Seong Soon Cho, Sunghoi Hur, Jintae Kang
  • Publication number: 20180366474
    Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.
    Type: Application
    Filed: July 26, 2018
    Publication date: December 20, 2018
    Inventors: TAEKYUNG KIM, KWANG SOO SEOL, SEONG SOON CHO, SUNGHOI HUR, JINTAE KANG
  • Patent number: 10043816
    Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: August 7, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kim Taekyung, Kwang Soo Seol, Seong Soon Cho, Sunghoi Hur, Jintae Kang
  • Publication number: 20170345907
    Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.
    Type: Application
    Filed: August 18, 2017
    Publication date: November 30, 2017
    Inventors: Kwang Soo Seol, Chanjin Park, Kihyun Hwang, Hanmei Choi, Sunghoi Hur, Wansik Hwang, Toshiro Nakanishi, Kwangmin Park, Juyul Lee
  • Patent number: 9831265
    Abstract: Provided is a semiconductor device including a substrate, gate electrodes vertically stacked on the substrate, insulating patterns between the gate electrodes, an active pillar provided to penetrate the gate electrodes and the insulating patterns and electrically coupled with the substrate, and a memory pattern provided between the gate electrodes and the active pillar and between the insulating patterns and the active pillar. The gate electrodes include edge portions extending between the memory pattern and the insulating patterns.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: November 28, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nambin Kim, Daewoong Kang, Dae Sin Kim, Kwang Soo Seol, Homin Son, Changsub Lee, Seunghyun Lim, Sunghoi Hur
  • Patent number: 9786675
    Abstract: A non-volatile memory device includes gate electrodes stacked on a substrate, a semiconductor pattern penetrating the gate electrodes and connected to the substrate, and a charge storage layer between the semiconductor pattern and the gate electrodes. The charge storage layer includes a first charge storage layer between the semiconductor pattern and the gate electrodes, a second charge storage layer between the first charge storage layer and the semiconductor pattern, and a third charge storage layer between the first charge storage layer and the gate electrodes. An energy band gap of the first charge storage layer is smaller than those of the second and third charge storage layers. The first charge storage layer is thicker than the second and third charge storage layers.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: October 10, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaehun Jung, Zhiliang Xia, Daewoong Kang, Dae Sin Kim, Kwang Soo Seol, Homin Son, Seunghyun Lim
  • Patent number: 9768266
    Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: September 19, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang Soo Seol, Chanjin Park, Kihyun Hwang, Hanmei Choi, Sunghoi Hur, Wansik Hwang, Toshiro Nakanishi, Kwangmin Park, Juyul Lee
  • Patent number: 9741735
    Abstract: A semiconductor device includes a stack comprising insulating patterns vertically stacked on a substrate and gate patterns interposed between the insulating patterns, an active pillar passing through the stack and electrically connected to the substrate and a charge storing layer interposed between the stack and the active pillar. The charge storing layer includes a first portion between the active pillar and one of the gate patterns, a second portion between the active pillar and one of the insulating patterns, and a third portion joining the first portion to the second portion and having a thickness less than that of the first portion.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: August 22, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Wook Lee, Daewoong Kang, Dae Sin Kim, Kwang Soo Seol, Homin Son, Seunghyun Lim
  • Patent number: 9640545
    Abstract: A non-volatile memory device can include a plurality of immediately adjacent offset vertical NAND channels that are electrically coupled to a single upper select gate line or to a single lower select gate line of the non-volatile memory device.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: May 2, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang Soo Seol, Sukpil Kim, Yoondong Park
  • Patent number: 9564499
    Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: February 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-Soo Seol, Chanjin Park, Ki-Hyun Hwang, Hanmei Choi, Sunghoi Hur, Wansik Hwang, Toshiro Nakanishi, Kwangmin Park, Ju-Yul Lee