Patents by Inventor Kwang Won Koh

Kwang Won Koh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10296379
    Abstract: Scheduling threads in a system with many cores includes generating a thread map where a connection relationship between a plurality of threads is represented by a frequency of inter-process communication (IPC) between threads, generating a core map where a connection relationship between a plurality of cores is represented by a hop between cores, and respectively allocating the plurality of threads to the plurality of cores defined by the core map, based on a thread allocation policy defining a mapping rule between the thread map and the core map.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: May 21, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kang Ho Kim, Kwang Won Koh, Jin Mee Kim, Jeong Hwan Lee, Seung Hyub Jeon, Sung In Jung, Yeon Jeong Jeong, Seung Jun Cha
  • Publication number: 20190138341
    Abstract: The preset specification provides a method of managing a disaggregated memory in a virtual system. Herein, the disaggregated memory managing method includes: detecting a memory access pattern in a virtual machine node based on an operation of a virtual machine; and performing a memory operation by using a memory block in consideration of the memory access pattern, wherein the memory access pattern is variably set based on a time at which the operation of the virtual machine is performed, and the memory block dynamically changes in size based on the memory access pattern.
    Type: Application
    Filed: November 9, 2018
    Publication date: May 9, 2019
    Inventors: Kwang Won KOH, Kang Ho KIM
  • Publication number: 20190114079
    Abstract: Disclosed is a method of managing a disaggregated memory. According to the present disclosure, the method includes: assigning at least one memory page to a local memory and a remote memory; checking a request for access to the memory page; checking whether a target performance ratio required in service is satisfied or not when the memory page requested to be accessed is assigned to the remote memory; predicting a size of the local memory on the basis of an LRU distance-based histogram when the target performance ratio is not satisfied; and reassigning the memory page requested to be accessed in consideration of the predicted size of the local memory.
    Type: Application
    Filed: October 16, 2018
    Publication date: April 18, 2019
    Applicants: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kang Ho KIM, Kwang Won KOH
  • Publication number: 20170329642
    Abstract: Provided is a many-core system including a resource unit including a resource needed for execution of an operating system and a resource needed for execution of a lightweight kernel, a programing constructing unit configured to convert an input program into an application program and to load the application program into the resource unit, a run-time management unit configured to manage a running environment for executing the application program, and a self-organization management unit configured to monitor the application program and the resources in the resource unit, to dynamically adjust the running environment to prevent a risk factor from occurring during the execution of the application program, and to cure a risk factor which occurred.
    Type: Application
    Filed: August 11, 2016
    Publication date: November 16, 2017
    Inventors: Jin Mee KIM, Kwang Won KOH, Kang Ho KIM, Jeong Hwan LEE, Seung Hyub JEON, Sung In JUNG, Yeon Jeong JEONG, Seung Jun CHA
  • Patent number: 9804903
    Abstract: Disclosed herein are a data processing apparatus for pipeline execution acceleration and a method thereof. According to an exemplary embodiment of the present invention, the data processing apparatus for pipeline execution acceleration includes: a processor configured to sequentially execute a first application program and a second application program reading or writing a specific file; and a file system configured to complete a write for a file data for the specific file to a data block previously allocated from the first application program and provide the file data for the specific file to the second application program prior to executing a close call for the specific file from the first application program, when executing a read call for the specific file from the second application program.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: October 31, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kang-Ho Kim, Kwang-Won Koh, Seung-Hyub Jeon
  • Publication number: 20170269966
    Abstract: Provided is a method of scheduling threads in a many-cores system. The method includes generating a thread map where a connection relationship between a plurality of threads is represented by a frequency of inter-process communication (IPC) between threads, generating a core map where a connection relationship between a plurality of cores is represented by a hop between cores, and respectively allocating the plurality of threads to the plurality of cores defined by the core map, based on a thread allocation policy defining a mapping rule between the thread map and the core map.
    Type: Application
    Filed: March 17, 2017
    Publication date: September 21, 2017
    Inventors: Kang Ho KIM, Kwang Won KOH, Jin Mee KIM, Jeong Hwan LEE, Seung Hyub JEON, Sung In JUNG, Yeon Jeong JEONG, Seung Jun CHA
  • Publication number: 20160371196
    Abstract: A memory management unit MMU for managing virtual memory for a plurality of cores includes a plurality of translation lookaside buffers TLBs each corresponding to each of the cores; a plurality of page tables each corresponding to each of the cores and to each of the TLBs, and each synchronized with a corresponding TLB, a meta page including virtual page-physical page mapping information included in the plurality of page tables, one of the plurality of page tables being a main page table; and the meta page including a shared bit field indicating whether or not the virtual page-physical page mapping information is stored in the plurality of TLBs.
    Type: Application
    Filed: June 9, 2016
    Publication date: December 22, 2016
    Inventor: Kwang Won KOH
  • Patent number: 9501394
    Abstract: Apparatus, method and systems for managing reference data, which can prevent duplicated data loading of reference data and eliminate redundancy of I/O operations for loading of the same reference data required by different virtual machines present in the same physical node to reduce use memory and I/O through sharing virtual machine leveled memories, are provided.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: November 22, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kwang-Won Koh, Kang-Ho Kim, Seung-Hyub Jeon, Seung-Jo Bae
  • Publication number: 20150356003
    Abstract: Apparatus, method and systems for managing reference data, which can prevent duplicated data loading of reference data and eliminate redundancy of I/O operations for loading of the same reference data required by different virtual machines present in the same physical node to reduce use memory and I/O through sharing virtual machine leveled memories, are provided.
    Type: Application
    Filed: June 9, 2015
    Publication date: December 10, 2015
    Inventors: Kwang-Won KOH, Kang-Ho KIM, Seung-Hyub JEON, Seung-Jo BAE
  • Patent number: 9189165
    Abstract: A method for memory management, include allocating an empty page of a physical memory for reference data according to execution of an application program, and mapping the empty page to a virtual memory; checking a physical address of the physical memory to which the reference data has been loaded; mapping the checked physical address to the virtual memory to which the empty page has been mapped, and mapping the reference data; and releasing allocation of the allocated physical memory when the reference data is mapped to the virtual memory.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: November 17, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kwang-Won Koh, Kang Ho Kim, Seung Hyub Jeon, Seungjo Bae
  • Patent number: 9164788
    Abstract: An automatic para-virtualization apparatus of an OS kernel is provided. The automatic para-virtualization apparatus includes a kernel profiler that detects profile information from a native OS kernel, and a virtualization unit that automatically generates a para-virtualized OS kernel that operates on a para-virtualization virtual machine monitor by combining the native OS kernel and the profile information.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: October 20, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kwang-Won Koh, Kang-Ho Kim, Soo-Cheol Oh, Chang-Won Ahn
  • Patent number: 9158562
    Abstract: Disclosed herein is a method and apparatus for supporting virtualization. In the method, conversion of source code of a loadable module is initiated. A virtualization-sensitive instruction is searched for during the conversion of the source code. If the virtualization-sensitive instruction has been found, a virtualization-sensitive instruction table is generated based on the found virtualization-sensitive instruction. The virtualization-sensitive instruction is substituted with an instruction recognizable in a privileged mode, based on the generated virtualization-sensitive instruction table. The loadable module is loaded and executed in a kernel. Accordingly, the present invention supports virtualization, thus minimizing overhead occurring in full virtualization, and guaranteeing the high performance provided by para-virtualization without modifying a source.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 13, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Seung-Hyub Jeon, Kwang-Won Koh, Kang-Ho Kim, Chei-Yol Kim, Chang-Won Ahn
  • Publication number: 20150254116
    Abstract: Disclosed herein are a data processing apparatus for pipeline execution acceleration and a method thereof. According to an exemplary embodiment of the present invention, the data processing apparatus for pipeline execution acceleration includes: a processor configured to sequentially execute a first application program and a second application program reading or writing a specific file; and a file system configured to complete a write for a file data for the specific file to a data block previously allocated from the first application program and provide the file data for the specific file to the second application program prior to executing a close call for the specific file from the first application program, when executing a read call for the specific file from the second application program.
    Type: Application
    Filed: February 9, 2015
    Publication date: September 10, 2015
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Kang-Ho KIM, Kwang-Won KOH, Seung-Hyub JEON
  • Patent number: 8966237
    Abstract: An OS switching method for switching an OS within several seconds in an information processing system is provided. In the information processing system which includes a processor, a main memory, a nonvolatile memory, and a plurality of input/output apparatuses, an OS switcher is executed when power is applied to the information processing system. When a first OS acquires an OS switch command that indicates a switch to a second OS while the first OS is activated and running, the first OS stores identification information of the second OS and information indicating an OS switch in the nonvolatile memory, and performs STR. The OS switcher switches an OS from the first OS to the second OS after the STR is completed. Accordingly, in the system, one OS can be quickly switched to another OS within several seconds, and a previous working environment can be maintained.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: February 24, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Soo Cheol Oh, Chang Won Ahn, Kang Ho Kim, Chei Yol Kim, Kwang Won Koh
  • Publication number: 20140310497
    Abstract: A method for memory management, include allocating an empty page of a physical memory for reference data according to execution of an application program, and mapping the empty page to a virtual memory; checking a physical address of the physical memory to which the reference data has been loaded; mapping the checked physical address to the virtual memory to which the empty page has been mapped, and mapping the reference data; and releasing allocation of the allocated physical memory when the reference data is mapped to the virtual memory.
    Type: Application
    Filed: July 15, 2013
    Publication date: October 16, 2014
    Inventors: Kwang-Won KOH, Kang Ho Kim, Seung Hyub Jeon, Seungjo Bae
  • Patent number: 8799895
    Abstract: A computing system for virtualization-based resource management includes a plurality of physical machines, a plurality of virtual machines and a management virtual machine. The virtual machines are configured by virtualizing each of the plurality of physical machines. The management virtual machine is located at any one of the plurality physical machines. The management virtual machine monitors amounts of network resources utilized by the plurality of physical machines and time costs of the plurality of virtual machines, and performs a resource reallocation and a resource reclamation.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: August 5, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Kwang Won Koh, Jin Mee Kim, Young Woo Jung, Young Choon Woo
  • Patent number: 8589143
    Abstract: A virtualization apparatus includes: an emulation manager for searching a basic block cache for an entry with an entry point, and, if there exists no entry with the entry point in the basic block cache, requesting the identification of a basic block corresponding to the entry point; a basic block identifier for identifying the basic block by sequentially analyzing instructions of a source binary in response to a request from the emulation manager; and an instruction replacer for writing an entry of the identified basic block in a replaced instruction table, writing a branch instruction for the entry of the basic block in the source binary, and then branching to the entry point. The apparatus further includes an instruction emulator for executing an instruction of the basic block when a branch to the entry point is made.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: November 19, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Kwang-Won Koh, Kang Ho Kim, Soo Cheol Oh, Ki-Hyuk Nam
  • Publication number: 20130139157
    Abstract: An automatic para-virtualization apparatus of an OS kernel is provided. The automatic para-virtualization apparatus includes a kernel profiler that detects profile information from a native OS kernel, and a virtualization unit that automatically generates a para-virtualized OS kernel that operates on a para-virtualization virtual machine monitor by combining the native OS kernel and the profile information.
    Type: Application
    Filed: August 29, 2012
    Publication date: May 30, 2013
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Kwang-Won KOH, Kang-Ho Kim, Soo-Cheol Ho, Chang-Won Ahn
  • Publication number: 20130054955
    Abstract: An OS switching method for switching an OS within several seconds in an information processing system is provided. In the information processing system which includes a processor, a main memory, a nonvolatile memory, and a plurality of input/output apparatuses, an OS switcher is executed when power is applied to the information processing system. When a first OS acquires an OS switch command that indicates a switch to a second OS while the first OS is activated and running, the first OS stores identification information of the second OS and information indicating an OS switch in the nonvolatile memory, and performs STR. The OS switcher switches an OS from the first OS to the second OS after the STR is completed. Accordingly, in the system, one OS can be quickly switched to another OS within several seconds, and a previous working environment can be maintained.
    Type: Application
    Filed: August 23, 2012
    Publication date: February 28, 2013
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Soo Cheol OH, Chang Won Ahn, Kang Ho Kim, Chei Yol Kim, Kwang Won Koh
  • Patent number: 8032780
    Abstract: Provided are a virtualization based high availability cluster system and a method for managing failures in a virtualization based high availability cluster system. The high availability cluster system includes a plurality of virtual nodes, and a plurality of physical nodes each including a message generator for generating a message denoting that the virtual nodes are in a normal state and transmitting the generated message to virtual nodes in a same physical node. One of the virtual nodes not included in a first physical node among the plurality of the physical nodes takes over resources related to a service if a failure is generated in one of virtual nodes included in the first physical node.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: October 4, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Kwang-Won Koh, Seungjo Bae, Jin Mee Kim, Young-Woo Jung, Young Choon Woo, Myung-Joon Kim