Abstract: Disclosed is a superjunction semiconductor device and a method for manufacturing the same and, more particularly, to a superjunction semiconductor device and a method for manufacturing the same seeking to improve a switching speed and thus to improve switching characteristics by reducing a gate-to-drain parasitic capacitance (Cgd) and/or configuring a gate electrode as a floating dummy gate.

Abstract: A gate electrode structure and a high voltage semiconductor device having the same are disclosed. The gate electrode structure includes a gate insulation layer pattern disposed on a substrate, a gate electrode disposed on the gate insulating layer pattern and having at least one opening at a first side portion thereof, and at least one insulating pattern disposed in the at least one opening. The high voltage semiconductor device includes a drift region disposed in the substrate adjacent to the first side portion of the gate electrode, a drain region electrically connected with the drift region, and a source region disposed in the substrate adjacent to a second side portion of the gate electrode.

Abstract: A semiconductor memory device and a method of fabricating the same which is suitable for fabrication of a non-volatile memory, such as an EEPROM, using a polysilicon-insulator-polysilicon (PIP) process. The semiconductor memory device includes isolation layers defining a tunneling region and a read transistor region of a semiconductor substrate, a lower polysilicon film formed on and/or over the tunneling region and the read transistor region, a dielectric film formed on and/or over the lower polysilicon film in the tunneling region, and an upper polysilicon film formed on and/or over the dielectric film.

Abstract: An electrically erasable programmable read only memory (EEPROM) is disclosed. The EEPROM includes a tunneling region in a semiconductor substrate, a control gate region in the semiconductor substrate and separated from the tunneling region by a device isolating layer, a tunnel oxide layer in a trench in the semiconductor substrate between the tunneling region and the control gate region, and a polysilicon layer on the tunnel oxide layer.

Abstract: A semiconductor device and a manufacturing method for the same are disclosed. The semiconductor device includes a gate pattern formed at an upper part of the semiconductor substrate to overlap one side of a drift region, and a shallow oxide region disposed adjacent to the gate pattern, having a shallower depth than a plurality of device isolation layers.

Abstract: A high voltage BICMOS device and a method for manufacturing the same, which may improve the reliability of the device by securing a distance between adjacent DUF regions, are provided. The high voltage BICMOS device includes: a reverse diffusion under field (DUF) region formed by patterning a predetermined region of a semiconductor substrate; a diffusion under field (DUF) region formed in the substrate adjacent to the reverse DUF region; a spacer formed at a sidewall of the reverse DUF region; an epitaxial layer formed on an entire surface of the substrate; and a well region formed in contact with the DUF region.

Abstract: Disclosed are a gate structure in a trench region of a semiconductor device and a method for manufacturing the same. The semiconductor device includes a pair of drift regions formed in a semiconductor substrate; a trench region formed between the pair of drift regions; an oxide layer spacer on sidewalls of the trench region; a gate formed in the trench region; and a source and a drain formed in the pair of the drift regions, respectively.

Abstract: A semiconductor device including a well region formed in a silicon substrate; a trench exposing a predetermined portion of the uppermost surface of the semiconductor substrate; a body layer formed in the semiconductor substrate at the trench; a device isolation layer formed in the well region; a gate insulating layer formed in the trench over the body layer; a gate electrode formed in the trench over the gate insulating layer and against the device isolation layer; a lightly doped drain region formed in the body layer; an insulating layer formed in the trench over the lightly doped drain region; a source region formed in the body layer; a drain region formed in the well region against the device isolation layer; and a body region formed in the body layer against the source region. The on-resistance can be reduced by forming the gate and source beneath the device isolating layer.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The method includes forming a collector region of a second conductivity type in a semiconductor substrate of a first conductivity type; forming a base region of the first conductivity type in the collector region, and forming an emitter region of the second conductivity type into the base region; forming an emitter in the emitter region, and forming a collector in the collector region; and forming a base in the semiconductor substrate through implanting high concentration impurity ions of the first conductive type into the semiconductor substrate.

Abstract: A semiconductor device includes a logic device and a LDMOS device. The logic device including a first well of a first conductive type formed in the substrate, a first source region and a first drain region formed in the first well, and a first gate electrode formed over the first well. The LDMOS device including a deep well of the first conductive type formed in a second substrate, a body region of a second conductive type and a second well of a first conductive type formed in the deep well, a second source region formed in the body region, a second drain region formed in the second well, a second gate electrode formed over the second substrate, and an impurity layer of the first conductive type formed in the second substrate under the second gate electrode.

Abstract: A semiconductor device and a manufacturing method for the same are disclosed. The semiconductor device includes a gate pattern formed at an upper part of the semiconductor substrate to overlap one side of a drift region, and a shallow oxide region disposed adjacent to the gate pattern, having a shallower depth than a plurality of device isolation layers.

Abstract: A trench gate semiconductor device, which is capable of securing a sufficient margin for a photo process while achieving an enhancement in gate-source leakage characteristics, is disclosed. Embodiments relate to a trench gate semiconductor device including an oxide film buffer filling a trench in an upper surface of an epitaxial layer over a semiconductor substrate; a gate poly formed in a gate trench, the gate trench extending from the oxide film buffer to the epitaxial layer; NPN junctions formed beneath the oxide film buffer at opposite sides of the gate poly; and poly plugs to electrically connect P type portions of the NPN junctions to upper metal electrodes.

Abstract: An electrically erasable programmable read only memory (EEPROM) is disclosed. The EEPROM includes a tunneling region in a semiconductor substrate, a control gate region in the semiconductor substrate and separated from the tunneling region by a device isolating layer, a tunnel oxide layer in a trench in the semiconductor substrate between the tunneling region and the control gate region, and a polysilicon layer on the tunnel oxide layer.

Abstract: A semiconductor memory device and a method of fabricating the same which is suitable for fabrication of a non-volatile memory, such as an EEPROM, using a polysilicon-insulator-polysilicon (PIP) process. The semiconductor memory device includes isolation layers defining a tunneling region and a read transistor region of a semiconductor substrate, a lower polysilicon film formed on and/or over the tunneling region and the read transistor region, a dielectric film formed on and/or over the lower polysilicon film in the tunneling region, and an upper polysilicon film formed on and/or over the dielectric film.

Abstract: Embodiments relate to a bipolar junction transistor and a method for manufacturing the same. An oxide pattern may be formed on a P type semiconductor substrate. A low-density N type collector area may be formed in the semiconductor substrate. First spacers may be formed at sidewalls of the oxide pattern, and a low-density P type base area may be formed in the semiconductor substrate. Second spacers may be formed on sidewalls of the first spacers. A high-density N type emitter area may be formed in the low-density P type base area between the second spacers, and a high-density N type collector area may be formed in the semiconductor substrate at an outside of the first spacers. The bipolar junction transistor may be realized through a self-aligned scheme using dual nitride spacers. A base width between the emitter area and the low-density collector area may be narrowed by the width of the second spacer.

Abstract: A biCMOS device including a bipolar transistor and a Polysilicon/Insulator/Polysilicon (PIP) capacitor is disclosed. A biCMOS device may have a relatively low series resistance at a bipolar transistor. A bipolar transistor may have a desirable amplification rate.

Abstract: A high voltage BICMOS device and a method for manufacturing the same, which may improve the reliability of the device by securing a distance between adjacent DUF regions, are provided. The high voltage BICMOS device includes: a reverse diffusion under field (DUF) region formed by patterning a predetermined region of a semiconductor substrate; a diffusion under field (DUF) region formed in the substrate adjacent to the reverse DUF region; a spacer formed at a sidewall of the reverse DUF region; an epitaxial layer formed on an entire surface of the substrate; and a well region formed in contact with the DUF region.

Abstract: A high voltage BICMOS device and a method for manufacturing the same, which may improve the reliability of the device by securing a distance between adjacent DUF regions, are provided. The high voltage BICOMOS device includes: a reverse diffusion under field (DUF) region formed by patterning a predetermined region of a semiconductor substrate; a diffusion under field (DUF) region formed in the substrate adjacent to the reverse DUF region; a spacer formed at a sidewall of the reverse DUF region; an epitaxial layer formed on an entire surface of the substrate; and a well region formed in contact with the DUF region.

Abstract: Disclosed are a gate structure in a trench region of a semiconductor device and a method for manufacturing the same. The semiconductor device includes a pair of drift regions formed in a semiconductor substrate; a trench region formed between the pair of drift regions; an oxide layer spacer on sidewalls of the trench region; a gate formed in the trench region; and a source and a drain formed in the pair of the drift regions, respectively.

Abstract: There is provided a high voltage semiconductor device comprising: a semiconductor substrate of a first conductivity type, including a first region, a second region relatively lower than the first region, and a sloped region between the first region and the second region; a drift region of a second conductivity type, formed on the second region; a source region of the second conductivity type, disposed on the first region, and spaced apart from the drift region by the sloped region; a drain region of the second conductivity type, disposed on the drift region; a field plate positioned on the drift region in the second region; a gate insulating layer disposed between the source region and the drift region; and a gate electrode layer, which is disposed on the gate insulating layer and extends to above the field plate.