Abstract: An apparatus for detecting an anomaly in an electronic system embodying at least two integrated circuits, and where necessary, removing/mitigating the anomaly. The anomaly detection is based on sensing the characteristics of either the current, the voltage, or both the current and voltage of the supply rail connected to the at least two integrated circuits. When an anomaly occurs, the anomaly is detected by one sensing circuit sensing that the characteristics are different from that when the electronic system is functioning normally.

Abstract: A device that includes one or more charging circuits is disclosed. Each charging circuit includes an input for connecting to an energy source, an output for connecting to an energy storage device, a signal generator and a switching circuit. The signal generator is configured to generate a control signal that includes enabling and disabling signal portions having a duty cycle that is based on an output voltage at the output. The switching circuit is configured to alternately couple the output to the input and a ground during the enabling signal portions of the control signal, and to isolate the output from the input and the ground during the disabling signal portions of the control signal. A method of charging an energy storage device is also disclosed.

Abstract: Various embodiments may provide an integrated circuit layout cell. The integrated circuit layout cell may include a doped region of a first conductivity type, a doped region of a second conductivity type opposite of the first conductivity type, and a further doped region of the first conductivity type at least partially within the doped region of the second conductivity type, and continuous with the doped region of the first conductivity type. The integrated circuit cell may include a first transistor having a control terminal, a first controlled terminal, and a second controlled terminal. The first controlled terminal and the second controlled terminal of the first transistor may include terminal regions of the second conductivity type formed within the further doped region of the first conductivity type. The integrated circuit cell may also include a second transistor.

Abstract: A circuit for mitigating single-effect-transients (SETs) comprising: a first sub-circuit comprising a first p-type transistor arrangement configured to generate a first output and a first n-type transistor arrangement configured to generate a second output; and a second sub-circuit comprising a connecting p-type transistor arrangement and a connecting n-type transistor arrangement connected in series, wherein the first output and the second output are electrically coupled to each other through the second sub-circuit.

Abstract: A control circuitry of a switched-mode power module, the switched-mode power module comprising a power stage configured to receive input power from a power supply and to output power to a load, the output power having an output voltage, the control circuitry configured to enable the power stage to output power when the output voltage is lower than a reference voltage by one of: a predetermined amount and an adaptive amount, the control circuitry further configured to disable the power stage from providing the output power when the output voltage exceeds the reference voltage by one of: a predetermined amount and an adaptive amount.

Abstract: A circuit arrangement is provided, having a first circuit configured to receive an input signal, and a second circuit configured to provide an output signal, wherein the first circuit includes a first pull-up network having a first transistor of a first conductivity type and a second transistor of a second conductivity type electrically coupled to each other, and a first pull-down network having a first transistor of the first conductivity type and a second transistor of the second conductivity type electrically coupled to each other, wherein the second circuit includes a second pull-up network having a first transistor of the first conductivity type, and a second pull-down network having a second transistor of the second conductivity type, wherein the first pull-up network and the second pull-down network are electrically coupled to each other, and wherein the first pull-down network and the second pull-up network are electrically coupled to each other.

Abstract: A method and an apparatus for hardware security to countermeasure side-channel attacks are provided. The method or apparatus may introduce at least one redundant or partial redundant computation having a similar power dissipation profile or an electromagnetic emission profile when compared to that of a genuine operation for cryptographic devices, and/or to reorder the iterations of operations in a different sequence. The redundant or partial redundant computation may be performed by using a different password key and/or a different raw data (e.g., plaintext). The presence of the redundant or partial redundant computation would make side-channel attacks difficult in the sense that genuine or redundant/partial redundant operations are difficult to be clearly identified, hence serving as a countermeasure for hardware security.

Abstract: According to embodiments of the present invention, a circuit is provided. The circuit includes a first set of transistors configured to receive one or more input signals provided to the circuit, and a second set of transistors electrically coupled to each other, wherein the second set of transistors is configured to provide one or more output signals of the circuit, wherein the first set of transistors and the second set of transistors are electrically coupled to each other, and wherein, for each transistor of the first set of transistors and the second set of transistors, the transistor is configured to drive a load associated with the transistor and has an aspect ratio that is sized larger than an aspect ratio of a transistor that is optimized for driving the load.

Abstract: A circuit arrangement is provided, having a first circuit configured to receive an input signal, and a second circuit configured to provide an output signal, wherein the first circuit includes a first pull-up network having a first transistor of a first conductivity type and a second transistor of a second conductivity type electrically coupled to each other, and a first pull-down network having a first transistor of the first conductivity type and a second transistor of the second conductivity type electrically coupled to each other, wherein the second circuit includes a second pull-up network having a first transistor of the first conductivity type, and a second pull-down network having a second transistor of the second conductivity type, wherein the first pull-up network and the second pull-down network are electrically coupled to each other, and wherein the first pull-down network and the second pull-up network are electrically coupled to each other.

Abstract: According to embodiments of the present invention, a circuit is provided. The circuit includes a first set of transistors configured to receive one or more input signals provided to the circuit, and a second set of transistors electrically coupled to each other, wherein the second set of transistors is configured to provide one or more output signals of the circuit, wherein the first set of transistors and the second set of transistors are electrically coupled to each other, and wherein, for each transistor of the first set of transistors and the second set of transistors, the transistor is configured to drive a load associated with the transistor and has an aspect ratio that is sized larger than an aspect ratio of a transistor that is optimized for driving the load.

Abstract: According to embodiments of the present invention, a circuit is provided. The circuit includes forming a first electrical device having a first region of a first conductivity type, forming a second electrical device having a second region of a second conductivity type, and electrically coupling the first region and the second region to each other, wherein one of the first and second regions is arranged to at least substantially surround the other of the first and second regions. According to further embodiments of the present invention, a method of forming a circuit is also provided.

Abstract: Various embodiments may provide an integrated circuit layout cell. The integrated circuit layout cell may include a doped region of a first conductivity type, a doped region of a second conductivity type opposite of the first conductivity type, and a further doped region of the first conductivity type at least partially within the doped region of the second conductivity type, and continuous with the doped region of the first conductivity type. The integrated circuit cell may include a first transistor having a control terminal, a first controlled terminal, and a second controlled terminal. The first controlled terminal and the second controlled terminal of the first transistor may include terminal regions of the second conductivity type formed within the further doped region of the first conductivity type. The integrated circuit cell may also include a second transistor.

Abstract: According to embodiments of the present invention, a circuit is provided. The circuit includes forming a first electrical device having a first region of a first conductivity type, forming a second electrical device having a second region of a second conductivity type, and electrically coupling the first region and the second region to each other, wherein one of the first and second regions is arranged to at least substantially surround the other of the first and second regions. According to further embodiments of the present invention, a method of forming a circuit is also provided.

Abstract: A method and an apparatus for hardware security to countermeasure side-channel attacks are provided. The method or apparatus may introduce at least one redundant or partial redundant computation having a similar power dissipation profile or an electromagnetic emission profile when compared to that of a genuine operation for cryptographic devices, and/or to reorder the iterations of operations in a different sequence. The redundant or partial redundant computation may be performed by using a different password key and/or a different raw data (e.g., plaintext). The presence of the redundant or partial redundant computation would make side-channel attacks difficult in the sense that genuine or redundant/partial redundant operations are difficult to be clearly identified, hence serving as a countermeasure for hardware security.

Abstract: A digital cell for performing a logic operation on a logic input to produce a logic output, includes an evaluation block and a sense-amplifier block, both configured to receive input signals representative of the logic input, and to detect when the logic input and/or input signals validly encode at least one bit. The digital cell is configured to alternate between an evaluate state and a reset state. Upon the digital cell being in the reset state and the detection, the digital cell is switched from the reset state to the evaluate state in which the evaluation block generates a difference in its output signals, and the sense-amplifier block amplifies the difference so that the output signals encode at least one valid bit. Upon the digital cell being in the evaluate state, the digital cell can be triggered to reset to the reset state.

Abstract: Pre-Charge Static Logic (PCSL), is an asynchronous-logic Quasi-Delay-Insensitive architecture based on Static-Logic, featuring fully-range Dynamic Voltage Scaling including robust operation in the sub-threshold voltage regime, with simultaneous low hardware overheads, high-speed and yet low power dissipation. The invented PCSL logic circuit achieves this by integration of the Request sub-circuit into the Static-Logic cell. During the initial phase, the output of Static-Logic cell (within the PCSL logic circuit) is pre-charged. During the evaluate phase, the Static-Logic cell computes the input and the PCSL logic circuit outputs the computation.

Abstract: Pre-Charge Static Logic (PCSL), is an asynchronous-logic Quasi-Delay-Insensitive architecture based on Static-Logic, featuring fully-range Dynamic Voltage Scaling including robust operation in the sub-threshold voltage regime, with simultaneous low hardware overheads, high-speed and yet low power dissipation. The invented PCSL logic circuit achieves this by integration of the Request sub-circuit into the Static-Logic cell. During the initial phase, the output of Static-Logic cell (within the PCSL logic circuit) is pre-charged. During the evaluate phase, the Static-Logic cell computes the input and the PCSL logic circuit outputs the computation.

Abstract: A digital Parallel Multiplier has a Partial Product Generator, a First Stage Adder Circuit and a Final Stage Adder Circuit. The spurious switching in the First Stage Adder Circuit may be substantially reduced by synchronizing the input signals to the Adders in First Stage Adder Circuit. The reduced spurious switching reduces the power dissipation of the Multiplier. The timing of the input signals is synchronized by means of the Latch Adders having a Latch that is an integral part of an Adder. Consequently, the power dissipation and hardware overheads of the Latch Adders are low. The Latch Adders may be controlled by Control Signals, which may be generated by Control Circuits. The application of the Latch Adders may be applied to the Final Stage Adder Circuit to further reduce spurious switching and thereby further reduce the power dissipation.

Abstract: A digital Parallel Multiplier having a Partial Product Generator (3), a First Stage Adder Circuit (71) and a Final Stage Adder Circuit (72), wherein the spurious switching in the First Stage Adder Circuit (71) may be substantially reduced by synchronizing the input signals to the Adders in First Stage Adder Circuit (71). The reduced spurious switching reduces the power dissipation of the Multiplier. The timing of the input signals is synchronized by means of the Latch Adders (41) having a Latch that is an integral part of an Adder. Consequently, the power dissipation and hardware overheads of the Latch Adders (41) are low. The Latch Adders (41) may be controlled by Control Signals (44), which may be generated by Control Circuits (61). The application of the Latch Adders (41) may be applied to the Final Stage Adder Circuit (72) to further reduce spurious switching and thereby further reduce the power dissipation.