Patents by Inventor Kwo-Hau Wu

Kwo-Hau Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of reducing thick film stress of spin-on dielectric and the resulting sandwich dielectric structure
    Patent number: 6903029
    Abstract: The present invention provides a technique to reduce a stress of thick spin-on dielectric layer by forming a sandwich dielectric structure, wherein a first dielectric layer is formed on a substrate by spin coating, a liquid phase deposited (LPD) silica layer is formed the first dielectric layer, and a second dielectric layer is formed on the LPD silica layer by spin coating. The LPD silica layer can be further subjected to a nitrogen plasma treatment to enhance its thermal stability and anti-water penetration ability.
    Type: Grant
    Filed: July 19, 2004
    Date of Patent: June 7, 2005
    Assignee: National Science Council
    Inventors: Ching-Fa Yeh, Yueh-Chuan Lee, Chih-Chuan Hsu, Kwo-Hau Wu, Shuo-Cheng Wang
  • Method of reducing thick film stress of spin-on dielectric and the resulting sandwich dielectric structure
    Publication number: 20040258932
    Abstract: The present invention provides a technique to reduce a stress of thick spin-on dielectric layer by forming a sandwich dielectric structure, wherein a first dielectric layer is formed on a substrate by spin coating, a liquid phase deposited (LPD) silica layer is formed the first dielectric layer, and a second dielectric layer is formed on the LPD silica layer by spin coating. The LPD silica layer can be further subjected to a nitrogen plasma treatment to enhance its thermal stability and anti-water penetration ability.
    Type: Application
    Filed: July 19, 2004
    Publication date: December 23, 2004
    Applicant: National Science Council
    Inventors: Ching-Fa Yeh, Yueh-Chuan Lee, Chih-Chuan Hsu, Kwo-Hau Wu, Shuo-Cheng Wang
  • Method of reducing thick film stress of spin-on dielectric and the resulting sandwich dielectric structure
    Patent number: 6774461
    Abstract: The present invention provides a technique to reduce a stress of thick spin-on dielectric layer by forming a sandwich dielectric structure, wherein a first dielectric layer is formed on a substrate by spin coating, a liquid phase deposited (LPD) silica layer is formed the first dielectric layer, and a second dielectric layer is formed on the LPD silica layer by spin coating. The LPD silica layer can be further subjected to a nitrogen plasma treatment to enhance its thermal stability and anti-water penetration ability.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: August 10, 2004
    Assignee: National Science Council
    Inventors: Ching-Fa Yeh, Yueh-Chuan Lee, Chih-Chuan Hsu, Kwo-Hau Wu, Shuo-Cheng Wang
  • Method of reducing thick film stress of spin-on dielectric and the resulting sandwich dielectric structure
    Publication number: 20020142580
    Abstract: The present invention provides a technique to reduce a stress of thick spin-on dielectric layer by forming a sandwich dielectric structure, wherein a first dielectric layer is formed on a substrate by spin coating, a liquid phase deposited (LPD) silica layer is formed the first dielectric layer, and a second dielectric layer is formed on the LPD silica layer by spin coating. The LPD silica layer can be further subjected to a nitrogen plasma treatment to enhance its thermal stability and anti-water penetration ability.
    Type: Application
    Filed: February 15, 2002
    Publication date: October 3, 2002
    Applicant: NATIONAL SCIENCE COUNCIL
    Inventors: Ching-Fa Yeh, Yueh-Chuan Lee, Chih-Chuan Hsu, Kwo-Hau Wu, Shuo-Cheng Wang
  • Semiconductor device having structure of copper interconnect/barrier dielectric liner/low-k dielectric trench and its fabrication method
    Patent number: 6294832
    Abstract: The present invention is related to a interconnection structure with Cu interconnects and low-k dielectric, in which a barrier dielectric liner made of a nitrogen-containing liquid-phase-deposition (LPD) fluorosilicate glass (FSG) film is used to replace a barrier metal layer and an oxide liner.
    Type: Grant
    Filed: April 10, 2000
    Date of Patent: September 25, 2001
    Assignee: National Science Council
    Inventors: Ching-Fa Yeh, Yueh-Chuan Lee, Kwo-Hau Wu, Yuh-Ching Su
  • Method of sidewall capping for degradation-free damascene trenches of low dielectric constant dielectric by selective liquid-phase deposition
    Patent number: 6251753
    Abstract: A low dielectric constant (k) material, such as methylsilsesquioxane (MSQ), used as an interlevel dielectric is expected to reduce the parasitic capacitance in integrated circuit. However, MSQ film can be easily degraded during resist ashing after the film is etched with the damascene trenches being created. The present invention discloses an innovative sidewall capping technology to solve the degradation issue. Prior to resist ashing, a high-quality, low-k oxide film is selectively deposited onto the sidewalls of MSQ trenches using selective liquid-phase deposition. Experimental results demonstrate that the capping oxide can effectively protect the sidewalls of MSQ trenches from ashing-induced degradation.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: June 26, 2001
    Inventors: Ching-Fa Yeh, Yueh-Chuan Lee, Yuh-Ching Su, Kwo-Hau Wu