Patents by Inventor Kwok Cheung Tsang

Kwok Cheung Tsang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7081403
    Abstract: A leadless plastic chip carrier is fabricated by selectively etching a leadframe strip to reduce a thickness of the strip at a portion thereof. Selectively masking the surface of the leadframe strip using a mask, follows selectively etching, to provide exposed areas of the surface at the portion and contact pad areas on leadframe the strip. At least one layer of metal is deposited on the exposed areas to define a die attach pad on the portion of the leadframe strip with reduced thickness and to define contact pads on the surface of the strip. At least one semiconductor die is mounted to the die attach pad, followed by wire bonding the at least one semiconductor die to ones of the contact pads. The at least one semiconductor die, the wire bonds, and the contact pads are covered with an overmold material and the leadframe strip is etched to thereby remove the leadframe strip. The leadless plastic chip carrier is singulated from the leadframe strip.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: July 25, 2006
    Assignee: ASAT Ltd.
    Inventors: Mohan Kirloskar, Chun Ho Fan, Kwok Cheung Tsang, Kin Pui Kwan
  • Patent number: 7009286
    Abstract: A leadless plastic chip carrier is fabricated by selectively etching a leadframe strip to reduce a thickness of the strip at a portion thereof. Selectively masking the surface of the leadframe strip using a mask, follows selectively etching, to provide exposed areas of the surface at the portion and contact pad areas on leadframe the strip. At least one layer of metal is deposited on the exposed areas to define a die attach pad on the portion of the leadframe strip with reduced thickness and to define contact pads on the surface of the strip. At least one semiconductor die is mounted to the die attach pad, followed by wire bonding the at least one semiconductor die to ones of the contact pads. The at least one semiconductor die, the wire bonds, and the contact pads are covered with an overmold material and the leadframe strip is etched to thereby remove the leadframe strip. The leadless plastic chip carrier is singulated from the leadframe strip.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: March 7, 2006
    Assignee: ASAT Ltd.
    Inventors: Mohan Kirloskar, Chun Ho Fan, Kwok Cheung Tsang, Kin Pui Kwan
  • Patent number: 6995460
    Abstract: A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, and an interlocking pattern for the die attach pad. After wire bonding and molding, a further etching is performed to isolate and expose contact pads. Singulation of individual chip packages from the leadframe strip is then performed by saw singulation or die punching.
    Type: Grant
    Filed: May 6, 2005
    Date of Patent: February 7, 2006
    Assignee: ASAT Ltd.
    Inventors: Neil McLellan, Chun Ho Fan, Kwok Cheung Tsang, Kin Pui Kwan, Wing Him Lau
  • Patent number: 6989294
    Abstract: A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, and an interlocking pattern for the die attach pad. After wire bonding and molding, a further etching is performed to isolate and expose contact pads. Singulation of individual chip packages from the leadframe strip is then performed by saw singulation or die punching.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: January 24, 2006
    Assignee: ASAT, Ltd.
    Inventors: Neil McLellan, Chun Ho Fan, Kwok Cheung Tsang, Kin Pui Kwan, Wing Him Lau
  • Patent number: 6964918
    Abstract: A process for fabricating an integrated circuit package includes establishing a plating mask on a first surface of a metal carrier. The plating mask defines a plurality of components including a die attach pad, at least one row of contact pads and at least one additional electronic component. A plurality of metallic layers are deposited on exposed portions of the first surface of the metal carrier. The plating mask is stripped from the metal carrier, leaving the plurality of metallic layers in the form of the plurality of components. A semiconductor die is mounted to die attach pad and pads of the semiconductor die are electrically connected to ones of the contact pads and to the additional electronic component. The first surface of the metal carrier is overmolded to encapsulate the plurality of components and the semiconductor die and the metal carrier is etched away.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: November 15, 2005
    Assignee: Asat Ltd.
    Inventors: Chun Ho Fan, Kwok Cheung Tsang
  • Patent number: 6933594
    Abstract: A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, and an interlocking pattern for the die attach pad. After wire bonding and molding, a further etching is performed to isolate and expose contact pads. Singulation of individual chip packages from the leadframe strip is then performed by saw singulation or die punching.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: August 23, 2005
    Assignee: ASAT Ltd.
    Inventors: Neil McLellan, Chun Ho Fan, Kwok Cheung Tsang, Kin Pui Kwan, Wing Him Lau
  • Patent number: 6872661
    Abstract: A leadless plastic chip carrier has a plurality of die attach pads on which a singulated semi-conductor die is mounted. At least one row of contact pads circumscribes the plurality of die attach pads and a power/ground ring is intermediate the contact pads and the die attach pads. Wire bonds connect the semiconductor die, the contact pads and the power/ground ring. An overmold covers the semi-conductor die, the die attach pads, the power/ground ring and the contact pads such that each of the die attach pads and the contact pads has one exposed surface.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: March 29, 2005
    Assignee: ASAT Ltd.
    Inventors: Kin Pui Kwan, Wing Him Lau, Kwok Cheung Tsang, Chun Ho Fan, Neil McLellan
  • Patent number: 6781242
    Abstract: An integrated circuit package is provided. The package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween. The substrate further has a cavity therein and a heat slug is fixed to the substrate and spans the cavity. A semiconductor die is mounted to the heat slug such that at least a portion of the semiconductor die is disposed in the cavity. A plurality of wire bonds connect the semiconductor die to ones of the conductive traces of the substrate and an encapsulating material encapsulates the wire bonds and the semiconductor die. A ball grid array is disposed on the first surface of the substrate. Bumps of the ball grid array are in electrical connection with ones of the conductive traces.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: August 24, 2004
    Assignee: ASAT, Ltd.
    Inventors: Chun Ho Fan, Kwok Cheung Tsang, William Lap Keung Chow
  • Patent number: 6635957
    Abstract: A leadless plastic chip carrier has a plurality of die attach pads on which a singulated semi-conductor die is mounted. At least one row of contact pads circumscribes the plurality of die attach pads and a power/ground ring is intermediate the contact pads and the die attach pads. Wire bonds connect the semiconductor die, the contact pads and the power/ground ring. An overmold covers the semiconductor die, the die attach pads, the power/ground ring and the contact pads such that each of the die attach pads and the contact pads has one exposed surface.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: October 21, 2003
    Assignee: ASAT Ltd.
    Inventors: Kin Pui Kwan, Wing Him Lau, Kwok Cheung Tsang, Chun Ho Fan, Neil Mclellan
  • Patent number: 6586834
    Abstract: An integrated circuit package including a flexible circuit tape having a flexible polyimide tape laminated to a conductor layer, a plurality of blind holes extending through the flexible tape to the conductor layer and a plurality of through holes extending through the flexible tape and the conductor layer. A copper leadframe is fixed to the flexible circuit tape and electrically isolated from the conductor layer. The copper leadframe includes an etched down die attach pad and heat spreader portions. The die attach pad is etched down such that at least a portion of the die attach pad is reduced in thickness. The through holes in the flexible circuit tape extend through to the copper leadframe. A semiconductor die is mounted on the at least a portion of the die attach pad. Wire bonds extend from pads on the semiconductor die to the die attach pad and from other pads on the semiconductor die to the conductor layer, an encapsulating material encapsulates the semiconductor die and the wire bonds.
    Type: Grant
    Filed: June 17, 2002
    Date of Patent: July 1, 2003
    Assignee: Asat Ltd.
    Inventors: Ming Wang Sze, Kwok Cheung Tsang, Wing Keung Lam, Kin-wai Wong
  • Patent number: 6429048
    Abstract: A method of fabricating an integrated circuit package for ball grid arrays, comprising the steps of: laminating layers of fiberglass prepreg and copper foil to a copper plate in order to create a three-layer laminated carrier; patterning and etching contact pads for input/output and a power/ground ring; applying a solder mask and plating up the contact pads and the ring with a wire bondable metal surface; forming window openings for receiving semiconductor dies; attaching the dies within the windows, wire bonding the dies to the contact pads and the ring, encapsulating the dies, attaching solder balls to the contact pads to create finished packages and singulating the finished packages into individual packages; and attaching the copper plate portion of each of the individual packages to copper plate heat spreader.
    Type: Grant
    Filed: December 5, 2000
    Date of Patent: August 6, 2002
    Assignee: ASAT Ltd.
    Inventors: Neil McLellan, Chun Ho Fan, Kwok Cheung Tsang, Pik Ling Lau
  • Publication number: 20020068378
    Abstract: A method of fabricating an integrated circuit package for ball grid arrays, comprising the steps of: laminating layers of fiberglass prepreg and copper foil to a copper plate in order to create a three-layer laminated carrier; patterning and etching contact pads for input/output and a power/ground ring; applying a solder mask and plating up the contact pads and the ring with a wire bondable metal surface; forming window openings for receiving semiconductor dies; attaching the dies within the windows, wire bonding the dies to the contact pads and the ring, encapsulating the dies, attaching solder balls to the contact pads to create finished packages and singulating the finished packages into individual packages; and attaching the copper plate portion of each of the individual packages to copper plate heat spreader.
    Type: Application
    Filed: December 5, 2000
    Publication date: June 6, 2002
    Applicant: ASAT Ltd.
    Inventors: Neil McLellan, Chun Ho Fan, Kwok Cheung Tsang, Pik Ling Lau
  • Publication number: 20010014538
    Abstract: A leadless plastic chip carrier has a plurality of die attach pads on which a singulated semi-conductor die is mounted. At least one row of contact pads circumscribes the plurality of die attach pads and a power/ground ring is intermediate the contact pads and the die attach pads. Wire bonds connect the semiconductor die, the contact pads and the power/ground ring. An overmold covers the semiconductor die, the die attach pads, the power/ground ring and the contact pads such that each of the die attach pads and the contact pads has one exposed surface.
    Type: Application
    Filed: March 9, 2001
    Publication date: August 16, 2001
    Applicant: ASAT Ltd.
    Inventors: Kin Pui Kwan, Wing Him Lau, Kwok Cheung Tsang, Chun Ho Fan, Neil Mclellan
  • Publication number: 20010008305
    Abstract: A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, and an interlocking pattern for the die attach pad. After wire bonding and molding, a further etching is performed to isolate and expose contact pads. Singulation of individual chip packages from the leadframe strip is then performed by saw singulation or die punching.
    Type: Application
    Filed: March 9, 2001
    Publication date: July 19, 2001
    Applicant: ASAT Ltd.
    Inventors: Neil McLellan, Chun Ho Fan, Kwok Cheung Tsang, Kin Pui Kwan, Wing Him Lau