Patents by Inventor Kwok Cheung

Kwok Cheung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110029147
    Abstract: A method is provided that enables dispatchers in power grid control centers to manage changes by applying multi-interval dispatch. A multi-stage resource scheduling engine and a comprehensive operating plan are used. Multiple system parameter scenarios are coordinated.
    Type: Application
    Filed: July 2, 2010
    Publication date: February 3, 2011
    Inventors: David Sun, Kwok Cheung, Xing Wang, But-Chung Chiu, Ying Xiao
  • Publication number: 20110029141
    Abstract: A method is provided for merging different load forecasts for power grid centers. Area load forecasts are accepted from load forecast engines. A relational database saves load forecast engine data. A comprehensive operating plan integrates individual load forecasts into a composite load forecast to present a comprehensive, synchronized and harmonized load forecast.
    Type: Application
    Filed: July 2, 2010
    Publication date: February 3, 2011
    Inventors: David Sun, Kwok Cheung, Kenneth Chung, Tory McKeag
  • Publication number: 20110029142
    Abstract: A system tool provides dispatchers in power grid control centers with a capability to manage changes. A user interface and a plurality of scheduler engines are provided. A comprehensive operating plan has multiple dispatch engines that are security constrained unit commitments and economic dispatch sequences with different look-ahead periods. The comprehensive operating plan is configured to integrate the dispatch engines into a unified scheduling system. The comprehensive operating plan has a data structure for capturing scheduling data, transaction scheduling, load forecast and time series data. The comprehensive operating plan is configured to coordinate scheduling data to and from power grid system applications and present a comprehensive, synchronized and harmonized view of scheduling data to at least one of, applications, power grid system operators and other stakeholders for power grid system operations.
    Type: Application
    Filed: July 2, 2010
    Publication date: February 3, 2011
    Inventors: David Sun, Kwok Cheung
  • Publication number: 20110022434
    Abstract: A method is provided for evaluating operational and financial performance for dispatchers in power grid control centers associated with utility systems. A comprehensive operating plan is provided that applies after the fact analysis for performance metrics, root-cause impacts and process re-engineering. after the fact analysis of past events and practices is performed. Actual system and resource conditions are captured. the system and resource conditions are supplied to a relational database. A scheduler engine receives the actual system and resource conditions from the relational database and processes it to calculate system performance.
    Type: Application
    Filed: July 2, 2010
    Publication date: January 27, 2011
    Inventors: David Sun, Kwok Cheung, But-Chung Chiu, Xing Wang, Ying Xiao, Kee Mok, Mike Yao
  • Publication number: 20100202165
    Abstract: A switching power converter comprises a transformer (110), a switch (108) coupled to the transformer (110), and a switch controller (200) coupled to the switch (108) for generating a switch drive signal (207) to turn on or off the switch (108). The drive current of the switch drive signal (207) is adjusted dynamically according to line or load conditions within a switching cycle and/or over a plurality of switching cycles. The magnitude of the drive current can be dynamically adjusted within a switching cycle and/or over a plurality of switching cycles, in addition to the pulse widths or pulse frequencies of the drive current.
    Type: Application
    Filed: September 28, 2007
    Publication date: August 12, 2010
    Applicant: IWATT INC.
    Inventors: Junjie Zheng, Jun Zheng, Andrew Kwok-Cheung Lee, John William Kesterson, Allan Ming-Lun Lin, Hien Huu Bui, Carrie Seim, Yong Li
  • Publication number: 20090077924
    Abstract: Methods for manufacturing an engineered wood product are disclosed. The method may include applying at least one preservative on the plurality of wood pieces; applying at least one resin on the plurality of wood pieces, wherein at least one of applying at least one preservative and applying at least one resin is configured to prevent interference among the at least one preservative and the at least one resin; forming a blanket of wood pieces from the plurality of wood pieces; and curing the at least one resin.
    Type: Application
    Filed: October 16, 2007
    Publication date: March 26, 2009
    Inventors: Kenneth Kwok-Cheung Lau, Christopher Clement Serbyn, Roger Lyle Summers
  • Patent number: 7482690
    Abstract: A process for fabricating an integrated circuit package includes establishing a plating mask on a first surface of a metal carrier. The plating mask defines a plurality of components including a die attach pad, at least one row of contact pads and at least one additional electronic component. A plurality of metallic layers is deposited on exposed portions of the first surface of the metal carrier. The plating mask is stripped from the metal carrier, leaving the plurality of metallic layers in the form of the plurality of components. A semiconductor die is mounted to die attach pad and pads of the semiconductor die are electrically connected to ones of the contact pads and to the additional electronic component. The first surface of the metal carrier is overmolded to encapsulate the plurality of components and the semiconductor die and the metal carrier is etched away.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: January 27, 2009
    Assignee: ASAT Ltd.
    Inventors: Chun Ho Fan, Kwok Cheung Tsang
  • Patent number: 7439099
    Abstract: An integrated circuit package is provided. The package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween. The substrate further has a cavity therein and a heat slug is fixed to the substrate and spans the cavity. A semiconductor die is mounted to the heat slug such that at least a portion of the semiconductor die is disposed in the cavity. A plurality of wire bonds connect the semiconductor die to ones of the conductive traces of the substrate and an encapsulating material encapsulates the wire bonds and the semiconductor die. A ball grid array is disposed on the first surface of the substrate. Bumps of the ball grid array are in electrical connection with ones of the conductive traces.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: October 21, 2008
    Assignee: ASAT Ltd.
    Inventors: Chun Ho Fan, Kwok Cheung Tsang, William Lap Keung Chow
  • Patent number: 7413076
    Abstract: A storage case for a generally planar item such as a compact disc. The case (10) has a pair of faces (12) adapted to distort when a compressive force is applied parallel to the plane of the disc (34). The case (10) also includes a retaining mechanism (14, 30) between the faces (12) that is adapted to hold the disc (34) in the case (10) when relaxed and adapted to urge the disc (34) out of the case (10) when the faces (12) are distorted by a force applied thereacross. Thus, the case (10) is easy to open and close and in the closed position protects the disc (34) from shock. Furthermore, a single action both opens the case (10) and offers the disc (34) out of the case for easy retrieval. The case (10) can also be adapted to clean the disc (34) as it is inserted into or withdrawn from the case.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: August 19, 2008
    Inventor: Jason Kwok Cheung
  • Publication number: 20080173413
    Abstract: There is disclosed a drape hangable, selectively, in differing configurations, the drape comprising: a plurality of fasteners secured at horizontally spaced intervals in an upper marginal region of the drape for releasably securing tabs for hanging the drape from a curtain rod; a plurality of curtain rod pockets secured at horizontally spaced intervals in the marginal region for receiving a curtain rod longitudinally inserted through a selected number of the curtain rod pockets; a plurality of tie loops secured at horizontally spaced intervals in the marginal region, each for receiving an associated tie for hanging the drape from a curtain rod. Kits for selectively hanging a drape in different configurations are also disclosed.
    Type: Application
    Filed: January 24, 2008
    Publication date: July 24, 2008
    Inventors: Randy Kwok Cheung LAM, Pansy Lee Ingvaldson
  • Patent number: 7372151
    Abstract: A process for manufacturing an integrated circuit package includes forming a plurality of solder balls on a first surface of a substrate and mounting a semiconductor die to the substrate such that bumps of the semiconductor die are electrically connected to conductive traces of the substrate. The semiconductor die and the solder balls are encapsulated in an overmold material on the substrate such that portions of the solder balls are exposed. A ball grid array is formed such that bumps of the ball grid array are electrically connected to the conductive traces and the integrated circuit package is singulated.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: May 13, 2008
    Assignee: ASAT Ltd.
    Inventors: Chun Ho Fan, Neil McLellan, Kwok Cheung Tsang
  • Patent number: 7358119
    Abstract: A process for fabricating an integrated circuit package. Metal is plated up on a substrate to provide a plurality of contact pads and a plurality of fiducial markings on a periphery of the contacts. A transparent mask is selectively deposited on the substrate, over the fiducial markings. A semiconductor die is mounted on the substrate such that the contact pads circumscribe the semiconductor die and the semiconductor die is wire bonded to ones of the contact pads. The wire bonds are encapsulated and the semiconductor die and contact pads are covered in a molding material. The substrate is selectively etched to thereby etch away the substrate underneath the contact pads and the semiconductor die. The integrated circuit package is singulated from other integrated circuit packages by sawing using the fiducial markings.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: April 15, 2008
    Assignee: Asat Ltd.
    Inventors: Neil McLellan, Serafin Pedron, Leo M. Higgins, III, Kwok Cheung Tsang, Kin Pui Kwan
  • Publication number: 20070287516
    Abstract: A wireless communication system based on a directional speaker is disclosed. The system can include an interface unit and a base unit. The audio signals from the speaker can be generated by transforming ultrasonic signals in air. This allows the production of directional audio signals even when the aperture of the speaker has dimensions in the order of a few centimeters. The audio signals from the speaker can be heard hands-free. Further, privacy protection is enhanced. In one embodiment, the interface unit can be attached or integrated to a piece of clothing at the shoulder of the user, with the audio signals from the speaker directed towards one of the user's ears. The wireless communication system can be applied to a number of different areas, including a communication device, such as a cell phone; a hearing aid; an entertainment system; and a computation system, such as a personal digital assistant or a computer.
    Type: Application
    Filed: August 16, 2007
    Publication date: December 13, 2007
    Inventors: Kwok Cheung, Peter Tong, C. Thomas
  • Patent number: 7271032
    Abstract: A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, and an interlocking pattern for the die attach pad. After wire bonding and molding, a further etching is performed to isolate and expose contact pads. Singulation of individual chip packages from the leadframe strip is then performed by saw singulation or die punching.
    Type: Grant
    Filed: May 6, 2005
    Date of Patent: September 18, 2007
    Assignee: ASAT Ltd.
    Inventors: Neil McLellan, Chun Ho Fan, Kwok Cheung Tsang, Kin Pui Kwan, Wing Him Lau
  • Patent number: 7270867
    Abstract: A process for fabricating a leadless plastic chip carrier includes selectively depositing a plurality of base layers on a first surface of a base of a leadframe strip to at least partially define a die attach pad and at least one row of contact pads. At least one further layer is selectively deposited on portions of the plurality of layers to further define at least the contact pads. The leadframe strip is then treated with a surface preparation. A semiconductor die is mounted to the die attach pad, followed by wire bonding the semiconductor die to at least the contact pads. Molding the semiconductor die, the wire bonds, the die attach pad and the contact pads on the surface of the leadframe strip, in a molding compound follows. The leadframe strip is etched to expose the contact pads and the die attach pad and the leadless plastic chip carrier is singulated from a remainder of the leadframe strip.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: September 18, 2007
    Assignee: ASAT Ltd.
    Inventors: Kin Pui Kwan, Wing Him Lau, Kwok Cheung Tsang, Chun Ho Fan, Neil McLellan
  • Patent number: 7232755
    Abstract: A process for fabricating a pad frame for an integrated circuit package includes building up metal on selective portions of a first side of a substrate to define a plurality of contact pads disposed in a first layer of dielectric material, depositing a metal seed layer on an exposed side of the contact pads and the dielectric material, applying a second metal layer on the metal seed layer, selectively etching the second metal layer and the metal seed layer to provide pad frame circuitry, and building up metal on selective portions of the pad frame circuitry to define a plurality of die connect pads separated by a second layer of dielectric material, the die connect pads being electrically connected to the contact pads by the pad frame circuitry.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: June 19, 2007
    Assignee: ASAT Ltd.
    Inventors: Neil McLellan, Chun Ho Fan, Kwok Cheung Tsang, Kin Pui Kwan
  • Publication number: 20060259565
    Abstract: A computer-implemented system and method to manage the communication of a user are disclosed. In one embodiment, when a person tries to electronically convey a message to the user, the status of the user, the identity of the person, and the urgency of the message can be identified. The access priority of the person can be determined based on the person's identity. Then, the message can be managed using one or more rules and in view of the status of the user, the access priority of the person and the urgency of the message.
    Type: Application
    Filed: June 12, 2006
    Publication date: November 16, 2006
    Inventors: Kwok Cheung, Peter Tong, C. Thomas
  • Publication number: 20060192050
    Abstract: A seating arrangement with improved seating comfort is disclosed. In one embodiment, the seating arrangement is for a transportation vehicle. The arrangement includes seats at least having two levels adjacent to single-level seats. The multi-level seats include at least a bottom row of seats and a top row of seats. In one embodiment, the bottom row seats are on a floor; and there is an imaginary horizontal plane that is parallel to the floor, and that at least a part of the top row seats and at least a part of the bottom row seats intersect. The single-level seats include at least two rows, with at least one seat in each row being adjacent to the aisle, to allow passengers to access the single-level seats. In another embodiment, a seating arrangement includes only multi-level seats. In yet another embodiment, a computer-implemented method is applicable to the seats, such as allowing the display of a visual representation of a top-row seat and a bottom-row seat.
    Type: Application
    Filed: February 28, 2006
    Publication date: August 31, 2006
    Inventors: Kwok Cheung, Peter Tong, C. Thomas
  • Patent number: 7081403
    Abstract: A leadless plastic chip carrier is fabricated by selectively etching a leadframe strip to reduce a thickness of the strip at a portion thereof. Selectively masking the surface of the leadframe strip using a mask, follows selectively etching, to provide exposed areas of the surface at the portion and contact pad areas on leadframe the strip. At least one layer of metal is deposited on the exposed areas to define a die attach pad on the portion of the leadframe strip with reduced thickness and to define contact pads on the surface of the strip. At least one semiconductor die is mounted to the die attach pad, followed by wire bonding the at least one semiconductor die to ones of the contact pads. The at least one semiconductor die, the wire bonds, and the contact pads are covered with an overmold material and the leadframe strip is etched to thereby remove the leadframe strip. The leadless plastic chip carrier is singulated from the leadframe strip.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: July 25, 2006
    Assignee: ASAT Ltd.
    Inventors: Mohan Kirloskar, Chun Ho Fan, Kwok Cheung Tsang, Kin Pui Kwan
  • Patent number: 7009286
    Abstract: A leadless plastic chip carrier is fabricated by selectively etching a leadframe strip to reduce a thickness of the strip at a portion thereof. Selectively masking the surface of the leadframe strip using a mask, follows selectively etching, to provide exposed areas of the surface at the portion and contact pad areas on leadframe the strip. At least one layer of metal is deposited on the exposed areas to define a die attach pad on the portion of the leadframe strip with reduced thickness and to define contact pads on the surface of the strip. At least one semiconductor die is mounted to the die attach pad, followed by wire bonding the at least one semiconductor die to ones of the contact pads. The at least one semiconductor die, the wire bonds, and the contact pads are covered with an overmold material and the leadframe strip is etched to thereby remove the leadframe strip. The leadless plastic chip carrier is singulated from the leadframe strip.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: March 7, 2006
    Assignee: ASAT Ltd.
    Inventors: Mohan Kirloskar, Chun Ho Fan, Kwok Cheung Tsang, Kin Pui Kwan