Patents by Inventor Kwok Fai Eng

Kwok Fai Eng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for evaluating decoupling capacitor placement for VLSI chips
    Patent number: 6618843
    Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: September 9, 2003
    Assignee: International Business Machines Corporation
    Inventors: Allan H. Dansky, Wiren D. Becker, Howard H. Smith, Peter J. Camporese, Kwok Fai Eng, Dale E. Hoffman, Bhupindra Singh
  • Method for evaluating decoupling capacitor placement for VLSI chips
    Patent number: 6618844
    Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: September 9, 2003
    Assignee: International Business Machines Corporation
    Inventors: Allan H. Dansky, Wiren D. Becker, Howard H. Smith, Peter J. Camporese, Kwok Fai Eng, Dale E. Hoffman, Bhupindra Singh
  • Contract methodology for concurrent hierarchical design
    Patent number: 6487706
    Abstract: A method for partitioning wiring connecting individual physical elements of a VLSI chip of a hierarchical design having multiple levels, begins by defining a size for the chip of a hierarchical design, and then removing blocked areas, including clock and power grid areas leaving the wiring channels available for interconnecting the individual elements of the VLSI chip. A percentage of the available area is allocated for wiring levels for global and local wiring as parallel iterations for the global and local wiring proceed and modified as the parallel iterations for the global and local wiring progress. During the parallel iterative process the number of wires increases for the power grid area to prevent a signal wire from having an active wire on either side of the signal wire. In the interactive process, a vertical slice of wiring resources used for the space above a macro entity is defined and the macro entity is checked with the context of the VLSI chip physical design above it.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: November 26, 2002
    Assignee: International Business Machines Corporation
    Inventors: Keith G. Barkley, Peter J. Camporese, Kwok Fai Eng
  • Method for evaluating decoupling capacitor placement for VLSI chips
    Publication number: 20020040467
    Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
    Type: Application
    Filed: June 29, 2001
    Publication date: April 4, 2002
    Applicant: INTERNATION BUSINESS MACHINES CORPORATION
    Inventors: Allan H. Dansky, Wiren D. Becker, Howard H. Smith, Peter J. Camporese, Kwok Fai Eng, Dale E. Hoffman, Bhupindra Singh
  • Method for evaluating decoupling capacitor placement for VLSI chips
    Publication number: 20020040463
    Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
    Type: Application
    Filed: June 29, 2001
    Publication date: April 4, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Allan H. Dansky, Wiren D. Becker, Howard H. Smith, Peter J. Camporese, Kwok Fai Eng, Dale E. Hoffman, Bhupindra Singh
  • Method for evaluating decoupling capacitor placement for VLSI chips
    Patent number: 6323050
    Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: November 27, 2001
    Assignee: International Business Machines Corporation
    Inventors: Allan H. Dansky, Wiren D. Becker, Howard H. Smith, Peter J. Camporese, Kwok Fai Eng, Dale E. Hoffman, Bhupindra Singh