Patents by Inventor Ky-Hyun Han

Ky-Hyun Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9728540
    Abstract: A semiconductor device includes a spacer having a nitride/oxide/nitride (NON) structure. The spacer is disposed between a sidewall of a bit line and a bit line contact and a sidewall of a storage node contact plug to reduce coupling capacitance between the bit line and a storage node contact plug and between the bit line contact and the storage node contact plug.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: August 8, 2017
    Assignee: SK HYNIX INC.
    Inventors: Ky Hyun Han, Chang Heon Park, Dong Gu Choi
  • Publication number: 20160322364
    Abstract: A semiconductor device includes a spacer having a nitride/oxide/nitride (NON) structure. The spacer is disposed between a sidewall of a bit line and a bit line contact and a sidewall of a storage node contact plug to reduce coupling capacitance between the bit line and a storage node contact plug and between the bit line contact and the storage node contact plug.
    Type: Application
    Filed: July 12, 2016
    Publication date: November 3, 2016
    Inventors: Ky Hyun HAN, Chang Heon PARK, Dong Gu CHOI
  • Patent number: 9419002
    Abstract: A semiconductor device includes a spacer having a nitride/oxide/nitride (NON) structure. The spacer is disposed between a sidewall of a bit line and a bit line contact and a sidewall of a storage node contact plug to reduce coupling capacitance between the bit line and a storage node contact plug and between the bit line contact and the storage node contact plug.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: August 16, 2016
    Assignee: SK HYNIX INC.
    Inventors: Ky Hyun Han, Chang Heon Park, Dong Gu Choi
  • Publication number: 20150235950
    Abstract: A semiconductor device includes a spacer having a nitride/oxide/nitride (NON) structure. The spacer is disposed between a sidewall of a bit line and a bit line contact and a sidewall of a storage node contact plug to reduce coupling capacitance between the bit line and a storage node contact plug and between the bit line contact and the storage node contact plug.
    Type: Application
    Filed: August 29, 2014
    Publication date: August 20, 2015
    Inventors: Ky Hyun HAN, Chang Heon PARK, Dong Gu CHOI
  • Patent number: 8592796
    Abstract: A phase-change random access memory device includes a semiconductor substrate, an interlayer dielectric layer formed over the semiconductor substrate and having contact holes defined therein, metal contacts formed in the contact holes, an ohmic contact layer formed over the metal contacts and having recesses defined therein, and switching elements formed over the recesses of the ohmic contact layer.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: November 26, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Myoung Sul Yoo, Jae Min Oh, Ky Hyun Han
  • Publication number: 20130240820
    Abstract: A method for fabricating a PCRAM includes forming a switching element on a semiconductor substrate, forming an interlayer dielectric layer of a multilayer-structure by sequentially stacking a plurality of material layers having different etching properties on the semiconductor substrate having the switching element formed thereon, and by patterning the plurality of material layers to have different lengths or different side shapes, forming a heating electrode on sidewalls of the interlayer dielectric layer and an upper surface of the switching element, and forming a phase change material layer to fill a space inside of the heating electrode.
    Type: Application
    Filed: April 26, 2013
    Publication date: September 19, 2013
    Applicant: SK hynix Inc.
    Inventors: Hee Seung SHIN, Ky Hyun HAN
  • Publication number: 20120326114
    Abstract: A phase-change random access memory device includes a semiconductor substrate, an interlayer dielectric layer formed over the semiconductor substrate and having contact holes defined therein, metal contacts formed in the contact holes, an ohmic contact layer formed over the metal contacts and having recesses defined therein, and switching elements formed over the recesses of the ohmic contact layer.
    Type: Application
    Filed: December 15, 2011
    Publication date: December 27, 2012
    Inventors: Myoung Sul YOO, Jae Min Oh, Ky Hyun Han
  • Publication number: 20120217219
    Abstract: A reference wafer maintains laser accuracy and calibrates a camera and a laser of a semiconductor equipment. The reference wafer includes a first anti-reflection layer, an adhesive layer, a light absorption layer and a second anti-reflection layer that are stacked over a substrate, a light reflection layer formed over the second anti-reflection layer, and a protection layer formed over the light reflection layer.
    Type: Application
    Filed: May 9, 2012
    Publication date: August 30, 2012
    Inventors: Hyun-Chul LEE, Jung-Taik Cheong, Gue-Hong Song, Ky-Hyun Han
  • Patent number: 8198626
    Abstract: A reference wafer maintains laser accuracy and calibrates a camera and a laser of a semiconductor equipment. The reference wafer includes a first anti-reflection layer, an adhesive layer, a light absorption layer and a second anti-reflection layer that are stacked over a substrate, a light reflection layer formed over the second anti-reflection layer, and a protection layer formed over the light reflection layer.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: June 12, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyun-Chul Lee, Jung-Taik Cheong, Gue-Hong Song, Ky-Hyun Han
  • Publication number: 20120025162
    Abstract: A method for fabricating a PCRAM includes forming a switching element on a semiconductor substrate, forming an interlayer dielectric layer of a multilayer-structure by sequentially stacking a plurality of material layers having different etching properties on the semiconductor substrate having the switching element formed thereon, and by patterning the plurality of material layers to have different lengths or different side shapes, forming a heating electrode on sidewalls of the interlayer dielectric layer and an upper surface of the switching element, and forming a phase change material layer to fill a space inside of the heating electrode.
    Type: Application
    Filed: December 22, 2010
    Publication date: February 2, 2012
    Inventors: Hee Seung SHIN, Ky-Hyun Han
  • Patent number: 7867911
    Abstract: A method for forming a pattern in a semiconductor device includes forming an etch target layer, forming a hard mask over the etch target layer, the hard mask including a multiple-layer stack structure comprising a bottom layer, a transformed layer, and an upper layer, wherein the transformed layer is formed by transforming a surface of the bottom layer. The hard mask and the etch target layer are etched.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: January 11, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ki-Won Nam, Ky-Hyun Han
  • Publication number: 20100295188
    Abstract: A semiconductor device having a deep contact structure having an improved contact resistance is presented. The semiconductor device includes a semiconductor substrate, a first interlayer insulating layer, a contact plug, a second interlayer insulating layer, and a copper contact pad. The contact plug is formed in the first interlayer insulating layer and has a bulbous shaped upper side wall and an inwardly tapered lower side wall that extends downward towards the semiconductor substrate. The second interlayer insulating layer is formed over first interlayer insulating layer such that the second interlayer insulating layer includes a hole that exposes a top surface and a peripheral portion of the bulbous shaped upper side wall of the contact plug. The copper contact pad is buried within the hole so that the exposed parts of the bulbous shaped upper side wall of the contact plug protrude into the copper contact pad.
    Type: Application
    Filed: December 11, 2009
    Publication date: November 25, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Ky Hyun HAN, Jae Min LEE
  • Publication number: 20100167064
    Abstract: A reference wafer maintains laser accuracy and calibrates a camera and a laser of a semiconductor equipment. The reference wafer includes a first anti-reflection layer, an adhesive layer, a light absorption layer and a second anti-reflection layer that are stacked over a substrate, a light reflection layer formed over the second anti-reflection layer, and a protection layer formed over the light reflection layer.
    Type: Application
    Filed: June 26, 2009
    Publication date: July 1, 2010
    Inventors: Hyun-Chul Lee, Jung-Taik Cheong, Gue-Hong Song, Ky-Hyun Han
  • Patent number: 7741223
    Abstract: A method for fabricating a semiconductor device includes etching a substrate to form a first recess having a micro trench, etching the substrate disposed under the first recess to form a second recess having a profile substantially vertical and a width greater than a portion of the first recess where no micro trench is formed, etching the substrate disposed under the second recess to form a third recess having a profile substantially spherical, and forming a gate pattern over a resultant recess including the first to third recesses.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: June 22, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyun-Sik Park, Ky-Hyun Han
  • Patent number: 7732335
    Abstract: A method for forming a semiconductor device includes forming an etch target layer, forming a sacrificial hard mask layer having a metal layer and a carbon-based material layer on the etch target layer, forming a photoresist pattern on the carbon-based material layer, etching the carbon-based material layer by the photoresist pattern until a remaining carbon-based material portion has a predetermined thickness, etching the remaining carbon-based material portion until a corresponding metal layer portion is exposed to form a carbon-based material pattern, and etching the metal layer by using the carbon-based material pattern to form a hard mask pattern for forming the pattern.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: June 8, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jung-Seock Lee, Ky-Hyun Han
  • Patent number: 7709369
    Abstract: A method for forming a contact in a semiconductor device includes opening a contact hole exposing a surface of a substrate, performing a first post treatment to form a rough portion at a bottom surface of the contact hole, and performing a second post treatment. The first post treatment includes using a fluorocarbon gas and the second post treatment includes using a nitrogen trifluoride (NF3) gas.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: May 4, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jung-Seock Lee, Ky-Hyun Han
  • Patent number: 7700455
    Abstract: A method for forming an isolation structure in a semiconductor device includes preparing a semi-finished substrate including a trench. An oxide layer is formed over sidewalls of the trench. A multiple layer structure of liner layers is formed over the oxide layer. An insulation layer is formed over the multiple layer structure such that the insulation layer fills an inside of the trench. The insulation layer is planarized.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: April 20, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ki-Won Nam, Ky-Hyun Han
  • Patent number: 7678535
    Abstract: A method for fabricating a semiconductor device includes forming a mask pattern over a substrate; etching a certain portion of the substrate using the mask pattern as an etch mask to form a first recess having sidewalls; forming a polymer-based layer over the sidewalls of the first recess and a top surface of the mask pattern; etching the substrate beneath the first recess using the mask pattern and the polymer-based layer as an etch mask to form a second recess wider and more rounded than the first recess, the second recess and the first recess constituting a bulb-shaped recess; and forming a gate pattern over the bulb-shaped recess.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: March 16, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Jung-Seock Lee, Ky-Hyun Han
  • Patent number: 7629242
    Abstract: A method for fabricating a semiconductor device having a recess gate includes forming a hard mask pattern on a substrate, etching the substrate using the hard mask pattern as an etch barrier to form a recess pattern, forming a passivation layer protecting surfaces of the recess pattern, etching a bottom surface of the recess pattern while protecting sidewalls of the recess pattern, performing an isotropic etching process onto a bottom portion of the recess pattern, and forming a gate pattern partially buried into the recess pattern after the isotropic etching process is performed.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: December 8, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ky-Hyun Han, Jung-Seock Lee
  • Patent number: 7615494
    Abstract: A method for fabricating a semiconductor device includes forming an insulation layer over a substrate, etching the insulation layer using a hard mask pattern to form a contact hole, filling the contact hole with a conductive layer, etching the conductive layer to form a plug in the contact hole, removing the remaining hard mask pattern to expose an upper portion of the plug and have the upper portion protrude above the insulation layer, and forming a metal line over the protruding plug and around the upper portion of the plug.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: November 10, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ky-Hyun Han, Ki-Won Nam