Abstract: An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.

Abstract: An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.

Abstract: An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.

Abstract: An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.

Abstract: An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.

Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically ove

Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically ove

Abstract: An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.

Abstract: An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.

Abstract: An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.

Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically ove

Abstract: An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.

Abstract: An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.

Abstract: An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.

Abstract: An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.

Abstract: A semiconductor device includes a substrate having a plurality of fins protruding therefrom. The plurality of fins includes a plurality of active fins and at least one non-active fin disposed between ones of the plurality of active fins. The device also includes at least one gate electrode crossing at least a portion of the active fins. The device further includes a plurality of source/drain regions disposed on the active fins adjacent the at least one gate electrode and separated from one another by the at least one non-active fin.

Abstract: An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.

Abstract: A semiconductor device includes a substrate having a plurality of fins protruding therefrom. The plurality of fins includes a plurality of active fins and at least one non-active fin disposed between ones of the plurality of active fins. The device also includes at least one gate electrode crossing at least a portion of the active fins. The device further includes a plurality of source/drain regions disposed on the active fins adjacent the at least one gate electrode and separated from one another by the at least one non-active fin.

Abstract: An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.

Abstract: An electrostatic chuck assembly, including an electrostatic chuck on which a substrate is loaded; a channel that provides a flow passage for coolant in the electrostatic chuck, the channel having a first opening at a first end corresponding to a center of the substrate and a second opening at a second end corresponding to an edge of the substrate; and a valve box to control a flow direction of the coolant in the channel, the valve box including a first supply valve to control an introduction of the coolant into the first opening; a first return valve to control a drainage of the coolant from the second opening; a second supply valve to control an introduction of the coolant into the second opening; and a second return valve to control a drainage of the coolant from the first opening.