Patents by Inventor Kye Nam Lee
Kye Nam Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8174879Abstract: A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing a plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a magnetization pair detection sensor including a MTJ (Magnetic Tunnel Junction) or GMR (Giant Magnetoresistive) device, a magnetoresistive sensor including a MTJ device and a magnetic material (current line), a dielectric constant sensor including a sensing capacitor and a switching device, a magnetization hole detection sensor including a MTJ or GMR device, a current line, a free ferromagnetic layer and a switching device, and a giant magnetoresistive sensor including a GMR device, a switching device and a magnetic material (or forcing wordline).Type: GrantFiled: October 26, 2009Date of Patent: May 8, 2012Assignee: Hynix Semiconductor Inc.Inventors: Hee Bok Kang, Dong Yun Jeong, Jae Hyoung Lim, Young Jin Park, Kye Nam Lee, In Woo Jang, Seaung Suk Lee, Chang Shuk Kim
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Patent number: 7825750Abstract: Disclosed relates to an electromagnetic interference (EMI) filter. Capacitance and resistance or inductance of an EMI filter, which includes a resistor and a capacitor or an inductor and a capacitor, can be controlled, such that a cutoff frequency can be freely controlled without manufacturing a separate EMI filter according to a characteristic of a desired cutoff frequency. Further, an intelligent EMI filter that can be applied to a surge protection device, which includes an ESD protection function as well as the EMI filter, is provided, such that a process can be simplified and costs can be reduced.Type: GrantFiled: June 27, 2007Date of Patent: November 2, 2010Assignee: Petari IncorporationInventors: Kye Nam Lee, Young Jin Park, Jin Hyung Kim, Hyun Kyu Yang, Yoo Ran Kim
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Publication number: 20100103720Abstract: A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a magnetization pair detection sensor including a MTJ (Magnetic Tunnel Junction) or GMR to (Giant Magnetoresistive) device, a magnetoresistive sensor including a MTJ device and a magnetic material (current line), a dielectric constant sensor including a sensing capacitor and a switching device, a magnetization hole detection sensor including a MTJ or GMR device, a current line, a free ferromagnetic layer and a switching device, and a giant magnetoresistive sensor including a GMR device, a switching device and a magnetic material (or forcing wordline).Type: ApplicationFiled: October 26, 2009Publication date: April 29, 2010Applicant: Hynix Semiconductor Inc.Inventors: Hee Bok KANG, Dong Yun Jeong, Jae Hyoung Lim, Young Jin Park, Kye Nam Lee, In Woo Jang, Seaung Suk Lee, Chang Shuk Kim
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Patent number: 7609547Abstract: A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing a plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a magnetization pair detection sensor including a MTJ (Magnetic Tunnel Junction) or GMR (Giant Magnetoresistive) device, a magnetoresistive sensor including a MTJ device and a magnetic material (current line), a dielectric constant sensor including a sensing capacitor and a switching device, a magnetization hole detection sensor including a MTJ or GMR device, a current line, a free ferromagnetic layer and a switching device, and a giant magnetoresistive sensor including a GMR device, a switching device and a magnetic material (or forcing wordline).Type: GrantFiled: December 21, 2007Date of Patent: October 27, 2009Assignee: Hynix Semiconductor Inc.Inventors: Hee Bok Kang, Dong Yun Jeong, Jae Hyoung Lim, Young Jin Park, Kye Nam Lee, In Woo Jang, Seaung Suk Lee, Chang Shuk Kim
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Publication number: 20090215259Abstract: Disclosed is a semiconductor package and a method of manufacturing the same. The semiconductor package includes a semiconductor chip that includes metal pads provided on a predetermined area of an upper side of a semiconductor substrate, where element structures used to manufacture a semiconductor element are formed, and bump electrodes connected to the metal pads; and a passivation film that is provided on an entire surface of the semiconductor chip other than upper surface of the bump electrodes. Therefore, it is possible to avoid difficulties in performing an epoxy underfill process used in a conventional flip chip bonding, and complexity and high cost resulting from the use of a molding compound process and a solder ball process. It is also possible to prevent damages to the lateral surface of the semiconductor chip due to an absence of the passivation film on the lateral surface of the semiconductor chip in a conventional wafer level package.Type: ApplicationFiled: April 3, 2009Publication date: August 27, 2009Applicants: PETARI INCORPORATIONInventors: Kye Nam LEE, Young Jin PARK, Hyun Kyu YANG, Yoo Ran KIM
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Patent number: 7572719Abstract: A method of manufacturing a semiconductor device is provided. The method includes: sequentially forming an oxide layer and a nitride layer on a substrate having a gate insulating layer and a gate formed in the order named thereon; forming a spacer at both sidewalls of the gate by etching the nitride layer; forming a source region and a drain region at both sides of the spacer in the substrate; removing the oxide layer formed on the gate and the substrate; partially removing surfaces of the gate, the source region and the drain region from which the oxide layer is removed; and depositing and thermally annealing a metal layer on the surfaces of the gate, source and drain whose surfaces are partially removed, to form a salicide layer.Type: GrantFiled: December 2, 2005Date of Patent: August 11, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Kye Nam Lee
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Patent number: 7452780Abstract: A method of forming a transistor includes: forming a gate oxide layer and a gate polysilicon layer on a silicon substrate; forming low-energy ion implantation regions in the silicon substrate and in alignment with both sidewalls of the gate polysilicon layer; forming gate spacers on both sidewalls of the gate polysilicon layer; forming amorphous layers on surfaces of the gate polysilicon layer and the silicon substrate by implanting impurities at a low implantation energy into the gate polysilicon layer and the silicon substrate; and forming high-energy ion implantation regions by implanting source/drain impurities at a high implantation energy into the silicon substrate including the gate polysilicon layer and the amorphous layer.Type: GrantFiled: December 29, 2005Date of Patent: November 18, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Kye-Nam Lee
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Patent number: 7432144Abstract: A method of forming a transistor including: forming a gate oxide layer pattern and gate polysilicon layer pattern on a silicon substrate; forming a low energy ion implantation region aligned with both sidewalls of the gate polysilicon layer pattern; forming an amorphous region at a lower part of both sidewalls of the gate polysilicon layer pattern; reducing a channel length by removing the amorphous region so as to form a notch at a lower part of both sidewalls of the gate polysilicon layer pattern; forming a gate spacer at both sidewalls of the gate polysilicon layer pattern; and forming a high energy ion implantation region by high energy ion implantation of source/drain impurities into an entire surface of the silicon substrate including the gate polysilicon layer pattern and gate spacer.Type: GrantFiled: December 30, 2005Date of Patent: October 7, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Kye-Nam Lee
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Patent number: 7333361Abstract: A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing a plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a magnetization pair detection sensor including a MTJ (Magnetic Tunnel Junction) or GMR (Giant Magnetoresistive) device, a magnetoresistive sensor including a MTJ device and a magnetic material (current line), a dielectric constant sensor including a sensing capacitor and a switching device, a magnetization hole detection sensor including a MTJ or GMR device, a current line, a free ferromagnetic layer and a switching device, and a giant magnetoresistive sensor including a GMR device, a switching device and a magnetic material (or forcing wordline).Type: GrantFiled: February 21, 2006Date of Patent: February 19, 2008Assignee: Hynix Semiconductor Inc.Inventors: Hee Bok Kang, Dong Yun Jeong, Jae Hyoung Lim, Young Jin Park, Kye Nam Lee, In Woo Jang, Seaung Suk Lee, Chang Shuk Kim
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Publication number: 20070296081Abstract: Disclosed is a semiconductor package and a method of manufacturing the same. The semiconductor package includes a semiconductor chip that includes metal pads provided on a predetermined area of an upper side of a semiconductor substrate, where element structures used to manufacture a semiconductor element are formed, and bump electrodes connected to the metal pads; and a passivation film that is provided on an entire surface of the semiconductor chip other than upper surface of the bump electrodes. Therefore, it is possible to avoid difficulties in performing an epoxy underfill process used in a conventional flip chip bonding, and complexity and high cost resulting from the use of a molding compound process and a solder ball process. It is also possible to prevent damages to the lateral surface of the semiconductor chip due to an absence of the passivation film on the lateral surface of the semiconductor chip in a conventional wafer level package.Type: ApplicationFiled: June 27, 2007Publication date: December 27, 2007Inventors: Kye Nam Lee, Young Jin Park, Hyun Kyu Yang, Yoo Ran Kim
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Publication number: 20070296277Abstract: Disclosed relates to an electromagnetic interference (EMI) filter. Capacitance and resistance or inductance of an EMI filter, which includes a resistor and a capacitor or an inductor and a capacitor, can be controlled, such that a cutoff frequency can be freely controlled without manufacturing a separate EMI filter according to a characteristic of a desired cutoff frequency. Further, an intelligent EMI filter that can be applied to a surge protection device, which includes an ESD protection function as well as the EMI filter, is provided, such that a process can be simplified and costs can be reduced.Type: ApplicationFiled: June 27, 2007Publication date: December 27, 2007Inventors: Kye Nam Lee, Young Jin Park, Jin Hyung Kim, Hyun Kyu Yang, Yoo Ran Kim
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Publication number: 20060148146Abstract: A method of forming a transistor including: forming a gate oxide layer pattern and gate polysilicon layer pattern on a silicon substrate; forming a low energy ion implantation region aligned with both sidewalls of the gate polysilicon layer pattern; forming an amorphous region at a lower part of both sidewalls of the gate polysilicon layer pattern; reducing a channel length by removing the amorphous region so as to form a notch at a lower part of both sidewalls of the gate polysilicon layer pattern; forming a gate spacer at both sidewalls of the gate polysilicon layer pattern; and forming a high energy ion implantation region by high energy ion implantation of source/drain impurities into an entire surface of the silicon substrate including the gate polysilicon layer pattern and gate spacer.Type: ApplicationFiled: December 30, 2005Publication date: July 6, 2006Applicant: DongbuAnam Semiconductor Inc.Inventor: Kye-Nam Lee
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Publication number: 20060148221Abstract: A method of forming a transistor includes: forming a gate oxide layer and a gate polysilicon layer on a silicon substrate; forming low-energy ion implantation regions in the silicon substrate and in alignment with both sidewalls of the gate polysilicon layer; forming gate spacers on both sidewalls of the gate polysilicon layer; forming amorphous layers on surfaces of the gate polysilicon layer and the silicon substrate by implanting impurities at a low implantation energy into the gate polysilicon layer and the silicon substrate; and forming high-energy ion implantation regions by implanting source/drain impurities at a high implantation energy into the silicon substrate including the gate polysilicon layer and the amorphous layer.Type: ApplicationFiled: December 29, 2005Publication date: July 6, 2006Inventor: Kye-Nam Lee
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Publication number: 20060121656Abstract: An example method of manufacturing a semiconductor device includes sequentially forming a gate insulating layer and a polysilicon layer on a semiconductor substrate having a first conductivity type, forming an amorphous silicon layer on a surface of the polysilicon layer by making the surface of the polysilicon layer amorphous, forming a crystallized polysilicon layer by respectively growing grains of the polysilicon layer and the amorphous silicon layer through a heat treatment process for the substrate, forming a gate by patterning the crystallized polysilicon layer, forming an LDD region having a second conductivity type in the substrate at both sides of the gate, forming a spacer at both sidewalls of the gate, and forming a source/drain region having the second conductivity type in the substrate at both sides of the spacer.Type: ApplicationFiled: December 1, 2005Publication date: June 8, 2006Inventor: Kye-Nam Lee
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Patent number: 7031186Abstract: A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing a plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a magnetization pair detection sensor including a MTJ (Magnetic Tunnel Junction) or GMR (Giant Magnetoresistive) device, a magnetoresistive sensor including a MTJ device and a magnetic material (current line), a dielectric constant sensor including a sensing capacitor and a switching device, a magnetization hole detection sensor including a MTJ or GMR device, a current line, a free ferromagnetic layer and a switching device, and a giant magnetoresistive sensor including a GMR device, a switching device and a magnetic material (or forcing wordline).Type: GrantFiled: August 29, 2003Date of Patent: April 18, 2006Assignee: Hynix Semiconductor Inc.Inventors: Hee Bok Kang, Dong Yun Jeong, Jae Hyoung Lim, Young Jin Park, Kye Nam Lee, In Woo Jang, Seaung Suk Lee, Chang Shuk Kim
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Patent number: 6930910Abstract: The present invention provides a magnetic random access memory (MRAM) cell device with a magnetic tunnel junction capable of obtaining a sufficient sense margins. To achieve this effect, the present invention provides a magnetic random access memory (MRAM) cell device, including: a word line; a bit line; a switching unit connected to the word line and the bit line; a magnetic tunnel junction unit connected to the bit line and the switching unit in parallel.Type: GrantFiled: December 3, 2002Date of Patent: August 16, 2005Assignee: Hynix Semiconductor Inc.Inventors: Sang-Hyun Oh, Kye-Nam Lee
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Patent number: 6927121Abstract: A method for manufacturing an FeRAM capacitor is employed to enhance an adhesive property between a dielectric layer and a first bottom electrode of iridium. The method including the steps of: preparing an active matrix including a semiconductor substrate, a transistor, a bit line, a first ILD, a second ILD and a storage node; forming a first bottom electrode on the second ILD and the storage node; forming a third ILD on exposed surfaces of the first bottom electrode and the second ILD; planarizing the third ILD till a top face of the first bottom electrode is exposed; forming a second bottom electrode on the top face of the bottom electrode; forming conductive oxides on exposed sidewalls of the first bottom electrode by carrying out an oxidation process; forming a dielectric layer on exposed surfaces of the first bottom electrodes, the second bottom electrode and the second ILD; and forming a top electrode on the dielectric layer.Type: GrantFiled: December 8, 2003Date of Patent: August 9, 2005Assignee: Hynix Semiconductor Inc.Inventors: Sang-Hyun Oh, Young-Ho Yang, Kye-Nam Lee, Suk-Kyoung Hong
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Patent number: 6919212Abstract: The present invention relates to a method for fabricating a ferroelectric random access memory (FeRAM) device. The method includes the steps of: forming a first inter-layer insulation layer on a substrate; forming a storage node contact connected with a partial portion of the substrate by passing through the first inter-layer insulation layer; forming a lower electrode connected to the storage node contact on the first inter-layer insulation layer; forming a second inter-layer insulation layer having a surface level lower than that of the lower electrode so that the second inter-layer insulation layer encompasses a bottom part of the lower electrode; forming an impurity diffusion barrier layer encompassing an upper part of the lower electrode on the second inter-layer insulation layer; forming a ferroelectric layer on the lower electrode and the impurity diffusion barrier layer; and forming a top electrode on the ferroelectric layer.Type: GrantFiled: December 18, 2003Date of Patent: July 19, 2005Assignee: Hynix Semiconductor Inc.Inventors: Sang-Hyun Oh, Kyu-Hyun Bang, In-Woo Jang, Jin-Yong Seong, Jin-Gu Kim, Song-Hee Park, Young-Ho Yang, Kye-Nam Lee, Suk-Kyoung Hong
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Patent number: 6914003Abstract: A method for manufacturing a magnetic random access memory is disclosed. An interlayer insulating film is formed on a lower read layer, a cell region of the interlayer insulating film is etched according to a photo etching process using a cell mask, and a MTJ layer is formed on the lower read layer of the cell region and the interlayer insulating film of a peripheral circuit region. The sidewall of the interlayer insulating film is exposed, the MTJ layer is left merely in the cell region by lifting off the interlayer insulating film, and a bit line which is an upper read layer connected to the MTJ layer is formed in a succeeding process. Accordingly, an effective area of an MTJ cell is obtained and the properties and reliability of the MRAM are improved.Type: GrantFiled: December 31, 2002Date of Patent: July 5, 2005Assignee: Hynix Semiconductor Inc.Inventors: Kye Nam Lee, Young Jin Park, Chang Shuk Kim, In Woo Jang, Hee Kyung
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Patent number: 6849468Abstract: The method for manufacturing an FeRAM capacitor having an enhanced adhesive property between a dielectric layer and a bottom electrode and a grain uniformity of the dielectric layer, is employed by forming hillocks on the bottom electrode purposefully before formation of the dielectric layer. The method includes steps of: preparing an active matrix obtained by predetermined processes; forming a first bottom electrode on the active matrix; forming a third ILD on exposed surfaces of the first bottom electrode and the second ILD; planarizing the third ILD till a top face of the first bottom electrode is exposed; forming a second bottom electrode on a top face of the bottom electrode; carrying out a first annealing process for deforming a surface of the second bottom electrode; forming a dielectric layer on exposed surfaces of the first bottom electrodes, the second bottom electrode and the third ILD; carrying out a second annealing process; and forming a top electrode on the dielectric layer.Type: GrantFiled: December 8, 2003Date of Patent: February 1, 2005Assignee: Hynix Semiconductor Inc.Inventors: In-Woo Jang, Jin-Yong Seong, Kye-Nam Lee, Suk-Kyoung Hong