Patents by Inventor Kyeongho Lee

Kyeongho Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240101181
    Abstract: A bearing and a steering apparatus including the same are provided. A bearing is disposed between a steering shaft and an inner column covering at least a part of the steering shaft. The bearing includes: an inner ring supporting an outer circumference of the steering shaft and having an elastically deformable material such as a plastic-containing material; an outer ring of which at least a part faces an inner circumference of the inner column; and a roller rotatably disposed between the inner ring and the outer ring.
    Type: Application
    Filed: August 25, 2023
    Publication date: March 28, 2024
    Inventor: Kyeongho LEE
  • Publication number: 20230420014
    Abstract: Embodiments of the present disclosure described herein relate to a computing in memory electronic device that supports current based analog operations and time based analog-to-digital conversion.
    Type: Application
    Filed: November 15, 2022
    Publication date: December 28, 2023
    Applicant: Korea University Research and Business Foundation
    Inventors: Jongsun PARK, Hyunchul PARK, Kyeongho LEE
  • Publication number: 20230395132
    Abstract: An SRAM cell includes a first pass gate transistor connected with a first word-line and a local bit-line, a first inverter that includes an output terminal connected with the first pass gate transistor and an input terminal, a second inverter that includes an input terminal connected with the first pass gate transistor and an output terminal, a second pass gate transistor connected with a second word line, the input terminal of the first inverter and the output terminal of the second inverter, and a complementary local bit-line, a first transistor connected with the second pass gate transistor, a local computing line, and a ground electrode, and a second transistor connected with a third word-line, the local computing line, and the ground electrode.
    Type: Application
    Filed: March 8, 2023
    Publication date: December 7, 2023
    Applicant: Korea University Research and Business Foundation
    Inventors: JONGSUN PARK, Kyeongho Lee, Hyunjun Kim
  • Publication number: 20230257018
    Abstract: A speed reducer for an electric power steering system according to an embodiment of the present disclosure includes a gear housing, a plurality of air flow passages, and check valves. The gear housing accommodates a worm shaft and a worm wheel. The plurality of air flow passages is formed in the gear housing and connects the outside of the gear housing and a sealed space formed in the gear housing. The check valves are respectively disposed in the plurality of air flow passages.
    Type: Application
    Filed: January 18, 2023
    Publication date: August 17, 2023
    Inventor: Kyeongho LEE
  • Patent number: 11664069
    Abstract: An in-memory computing device includes a memory cell array and a column peripheral circuit including a plurality of column peripheral units connected to a plurality of pairs of bit lines connected to the memory cell array. Each of the column peripheral units includes a sense amplifying and writing unit sensing and amplifying bitwise data through one pair of bit lines among the pairs of bit lines and an arithmetic logic unit performing an arithmetic operation with a full adder Boolean equation based on the bitwise data and performing a write back operation on operation data obtained by the arithmetic operation via the sense amplifying and writing unit.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: May 30, 2023
    Assignee: Korea University Research and Business Foundation
    Inventors: Jongsun Park, Kyeongho Lee, Woong Choi
  • Patent number: 11626159
    Abstract: A computing in-memory device includes a memory cell array supporting a bitwise operation through at least one pair of memory cells activated in response to at least one pair of word line signals and a peripheral circuit connected to the at least one pair of memory cells via one pair of bit lines and performing a discharging operation on at least one bit line of the one pair of bit lines based on a voltage level of the one pair of bit lines.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: April 11, 2023
    Assignee: Korea University Research and Business Foundation
    Inventors: Jongsun Park, Kyeongho Lee, Woong Choi
  • Publication number: 20220379952
    Abstract: The present disclosure provides a driving unit of a steering apparatus configured to provide an auxiliary torque of a steering apparatus and including a driving housing having an installation region formed therein, and the driving unit includes a worm shaft disposed in the installation region and having a worm gear formed therein, a first bearing rotatably supporting one side of the worm shaft, a damper penetrating and supporting one side of the worm shaft supported by the first bearing, and a stopper penetrating and supporting one side of the worm shaft passing through the damper, one end of the stopper being spaced apart from the damper so that a movement of the damper is limited in an axial direction of the worm shaft.
    Type: Application
    Filed: May 4, 2022
    Publication date: December 1, 2022
    Inventors: Bong Sung KO, Kyeongho LEE
  • Publication number: 20220242477
    Abstract: The present disclosure is direction to a stopper disposed in a driver for a steering apparatus which includes a worm gear, a bearing supporting rotation of the worm gear, and a damper buffering an impact of the bearing is provided, the stopper including: an annular body having a through hole therein allowing one side of the worm gear to pass through; and a leg on the annular body to protrude toward the damper along an axial direction of the worm gear.
    Type: Application
    Filed: January 18, 2022
    Publication date: August 4, 2022
    Inventor: Kyeongho LEE
  • Publication number: 20220028445
    Abstract: An in-memory computing device includes a memory cell array and a column peripheral circuit including a plurality of column peripheral units connected to a plurality of pairs of bit lines connected to the memory cell array. Each of the column peripheral units includes a sense amplifying and writing unit sensing and amplifying bitwise data through one pair of bit lines among the pairs of bit lines and an arithmetic logic unit performing an arithmetic operation with a full adder Boolean equation based on the bitwise data and performing a write back operation on operation data obtained by the arithmetic operation via the sense amplifying and writing unit.
    Type: Application
    Filed: July 16, 2021
    Publication date: January 27, 2022
    Applicant: Korea University Research and Business Foundation
    Inventors: Jongsun PARK, Kyeongho LEE, Woong CHOI
  • Publication number: 20210391001
    Abstract: A computing in-memory device includes a memory cell array supporting a bitwise operation through at least one pair of memory cells activated in response to at least one pair of word line signals and a peripheral circuit connected to the at least one pair of memory cells via one pair of bit lines and performing a discharging operation on at least one bit line of the one pair of bit lines based on a voltage level of the one pair of bit lines.
    Type: Application
    Filed: June 2, 2021
    Publication date: December 16, 2021
    Applicant: Korea University Research and Business Foundation
    Inventors: Jongsun PARK, Kyeongho LEE, Woong CHOI
  • Patent number: 8243579
    Abstract: Embodiments according to the application relates to an OFDM (orthogonal frequency division multiplexing) receiving circuit and methods thereof configured to have a plurality of demodulation paths for an oversampling ADC, which can increase or improve an overall performance of the circuit.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: August 14, 2012
    Assignee: GCT Semiconductor, Inc.
    Inventors: Seung-Wook Lee, Joonbae Park, Jeong Woo Lee, Su Won Kang, Kyeongho Lee
  • Patent number: 8229028
    Abstract: The present invention relates to an apparatus and a method for measuring an in phase and quadrature (IQ) imbalance. One embodiment according to the present general inventive concept can provide a method for measuring a Tx IQ imbalance generated in an IQ up-conversion mixer and an Rx IQ imbalance generated in an IQ down-conversion mixer, that includes measuring a first IQ imbalance corresponding to a first combination of the Rx IQ imbalance with the Tx IQ imbalance, measuring a second IQ imbalance corresponding to a second combination of the Rx IQ imbalance with the Tx IQ imbalance and obtaining the Tx IQ imbalance and the Rx IQ imbalance from the first IQ imbalance and the second IQ imbalance.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: July 24, 2012
    Assignee: GCT Semiconductor, Inc.
    Inventors: Kyeongho Lee, Joonbae Park, Jeong Woo Lee, Seung-Wook Lee, Eal Wan Lee
  • Patent number: 8018990
    Abstract: The present general inventive concept relates to apparatuses and/or methods for measuring an in-phase and quadrature (IQ) imbalance. In one embodiment, a detector can measure an error caused by an IQ imbalance using a first IQ signal including a desired signal and a corresponding image signal by the IQ imbalance. The detector can include a derotator to derotate the first IQ signal by a first angular frequency to obtain a second IQ signal and derotate the first IQ signal by a second angular frequency to obtain a third IQ signal, a DC estimator to obtain a fourth IQ signal corresponding to a DC component of the second IQ signal and a fifth IQ signal corresponding to a DC component of the third IQ signal and a controller can determine a gain error or a phase error from the fourth IQ signal and the fifth IQ signal.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: September 13, 2011
    Assignee: GCT Semiconductor, Inc.
    Inventors: Kyeongho Lee, Joonbae Park, Jeong Woo Lee, Seung-Wook Lee, Eal Wan Lee
  • Patent number: 7995645
    Abstract: The present general inventive concept relates to apparatuses and/or methods for measuring an in-phase and quadrature (IQ) imbalance. In one embodiment, a signal generator can provide a first IQ signal of a DC component during a first period and the first IQ signal of a first angular frequency during a second period, an IQ up-conversion mixer can up-convert the first IQ signal by a second angular frequency during the first period and up-convert the first IQ signal by a third angular frequency during the second period to output a second IQ signal, an IQ down-conversion mixer can down-convert the second IQ signal by the third angular frequency to output a third IQ signal and an IQ imbalance detector can obtain a first IQ imbalance (e.g., Rx IQ imbalance) from the third IQ signal during the first period and a second IQ imbalance (e.g., Tx/Rx IQ imbalance) during the second period.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: August 9, 2011
    Assignee: GCT Semiconductor, Inc.
    Inventors: Kyeongho Lee, Joonbae Park, Jeong Woo Lee, Seung-Wook Lee, Eal Wan Lee
  • Patent number: 7952442
    Abstract: An integrated circuit package includes an inductance loop formed from a connection of bonding wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a bonding pad on the integrated circuit chip to an I/O pin of the package and a second wire which connects the same bonding pad to the same pin. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: May 31, 2011
    Assignee: GCT Semiconductor, Inc.
    Inventors: Yido Koo, Hyungki Huh, Kang Yoon Lee, Jeong-Woo Lee, Joonbae Park, Kyeongho Lee
  • Patent number: 7952435
    Abstract: Embodiments of a phase lock loop and a method for compensating a temperature thereof can output an initial tuning digital value for a voltage controlled oscillator configured to output a desired phase lock loop frequency compensated according to a temperature change. Embodiments of a phase lock loop and a method for compensating a temperature thereof can simultaneously perform a digital coarse tuning and an analog fine tuning to compensate for a temperature in a limited time.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: May 31, 2011
    Assignee: GCT Semiconductor, Inc.
    Inventors: Seung-Wook Lee, Joonbac Park, Jeong Woo Lee, Su Won Kang, Kyeongho Lee
  • Patent number: 7949324
    Abstract: The application discloses embodiments of methods and/or systems for compensating a transmission carrier leakage of an up-conversion mixer, a tranceiving circuit or apparatus embodying the same. One embodiment of a method can include detecting an I channel DC offset DCI0 and a Q channel DC offset DCQ0 generated by a reception carrier leakage from an output of a down-conversion mixer, detecting an I channel DC offset DCI and a Q channel DC offset DCQ from the output of the down-conversion mixer while varying a compensation parameter being inputted to an up-conversion mixer that has its output coupled to an input of the down-conversion mixer to determine the compensation parameter that can reduce or minimize a transmission carrier leakage. A combination of a transmission baseband signal and the determined compensation parameter can be transmitted using the up-conversion mixer and an antenna to compensate for the transmission carrier leakage.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: May 24, 2011
    Assignee: GCT Semiconductor, Inc.
    Inventors: Joonbae Park, Kyeongho Lee, Sang Hun Jung, Eal Wan Lee, In Ho Song
  • Patent number: 7945208
    Abstract: Embodiments of an RFIC and methods for same and mobile terminals can internally reduce an input voltage to provide a prescribed voltage to a radio frequency transceiver. Embodiments of an RFIC can have a high efficiency and/or a low noise. In one embodiment, a device can include a PMIC and an RFIC. The RFIC can include an RF transceiver to carry out an RF transmission and an RF reception, a DC-DC converter to lower a voltage provided by the PMIC, and an LDO regulator to regulate the lowered voltage to a fixed voltage used by the RF transceiver.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: May 17, 2011
    Assignee: GCT Semiconductor, Inc.
    Inventors: Joonbae Park, Kyeongho Lee, Yido Koo, Jeong Woo Lee
  • Patent number: 7925217
    Abstract: Embodiments of methods receiving circuits and apparatuses compensate for an IQ mismatch using a test signal positioned in a guard band. One embodiment of a method can include converting a sum of a received signal and a test signal positioned in a guard band to a first signal and a second signal of an intermediate frequency or a base band using an IQ mixer, detecting the IQ mismatch using the test signal respectively included in subsequent signals corresponding to the first signal and the second signal and compensating for the detected IQ mismatch using the IQ mismatch.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: April 12, 2011
    Assignee: GCT Research, Inc.
    Inventors: Joonbae Park, Kyeongho Lee
  • Patent number: 7831215
    Abstract: Embodiments of methods, transceiver circuits, and systems can compensate an IQ mismatch (e.g., Tx or Rx) or a carrier leakage using a plurality of local oscillators. One embodiment of a transceiver can include a first up-conversion IQ mixer, a second up-conversion IQ mixer, a first down-conversion IQ mixer with an input to receive an output of the second up-conversion IQ mixer, a second down-conversion IQ mixer with an input to receive an output of the first up-conversion IQ mixer, a first local oscillator to generate a first IQ LO signal for the first up-conversion IQ mixer and the first down-conversion IQ mixer, and a second local oscillator to generate a second IQ LO signal for the second up-conversion IQ mixer and the second down-conversion IQ mixer.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: November 9, 2010
    Assignee: GCT Research, Inc.
    Inventors: Joonbae Park, Kyeongho Lee