Abstract: A method of preparing a bimodal positive electrode active material precursor and a positive electrode active material prepared from the same are disclosed herein. In some embodiments, the method includes inputting a first reaction source material including a first aqueous transition metal solution into a reactor, precipitating at pH 12 or more to induce nucleation of a first positive electrode active material precursor particle, and at less than pH 12 to induce growth of the same, inputting a second reaction source material including a second aqueous transition metal solution into the reactor containing the first positive electrode active material precursor particle, precipitating at pH 12 or more to induce the nucleation of a second positive electrode active material precursor particle, and at less than pH 12 to induce simultaneous growth of the first and second positive electrode active material precursor particles, thereby preparing a bimodal positive electrode active material precursor.

Abstract: A method for preparing a positive electrode active material precursor includes preparing a metal aqueous solution including a nickel raw material, a cobalt raw material, and a manganese raw material (step 1); adding the metal aqueous solution, an ammonium cation complex forming agent, and a basic aqueous solution into a reactor, co-precipitating the mixture at pH 11 to less than pH 12 to form nuclei of first positive electrode active material precursor particles and growing the nuclei (step 2); adjusting input amount of the basic aqueous solution to increase the pH in the reactor to a range of 0.8 to 1.5 compared to that of step 2; and adjusting input amount of the basic aqueous solution to change the pH in the reactor to pH 11 to less than pH 12 (step 4). A positive electrode active material precursor prepared by the above preparation method has an improved packing density.

Abstract: A method for preparing a bimodal-type positive electrode active material precursor is provided. The method is capable of not only increasing productivity by preparing positive electrode active material precursors having small diameters and large diameters in a single reactor but also improving packing density per unit volume, a positive electrode active material precursor prepared by the preparation method and having improved packing density, and a positive electrode for a secondary battery and a lithium secondary battery including the same.

Abstract: A cleaning method according to the present invention comprises mounting the metal filter on a jig that is vertically elevatable and horizontally slidable in a cleaning bath so that the opening is faced downward, descending the jig so that a first nozzle installed in the cleaning bath enters the opening, injecting a predetermined amount of water and a cleaning solution into the cleaning bath so that the metal filter is immersed, spraying compressed air through the first nozzle to discharge bubbles of the compressed air toward an inner surface of the metal filter, draining the cleaning bath, spraying water through a second nozzle to remove the cleaning solution from the metal filter, and spraying the compressed air through the first nozzle to dry the metal filter. An apparatus for cleaning a metal filter is also disclosed.

Abstract: Provided is an apparatus for producing a positive electrode active material precursor. The apparatus includes: a reactor into which a reaction solution is introduced; a stirrer being inserted into the reactor and stirring the reaction solution; and a filter type baffle being inserted into the reactor and including a filter.

Abstract: A positive electrode active material precursor having a uniform particle size distribution and represented by Formula 1, wherein a percentage of fine powder with an average particle diameter (D50) of 1 ?m or less is generated when the positive electrode active material precursor is rolled at 2.5 kgf/cm2 is less than 1%, and an aspect ratio is 0.93 or more, and a method of preparing the positive electrode active material precursor [NixCoyM1zM2w](OH)2??[Formula 1] in Formula 1, 0.5?x<1, 0<y?0.5, 0<z?0.5, and 0?w?0.1, M1 includes at least one selected from the group consisting of Mn and Al, and M2 includes at least one selected from the group consisting of Zr, B, W, Mo, Cr, Nb, Mg, Hf, Ta, La, Ti, Sr, Ba, Ce, F, P, S, and Y. A method of preparing the positive electrode active material precursor is also provided.

Abstract: A co-precipitation reactor with a continuous filtering system mounted, wherein the co-precipitation reactor includes a main body accommodating a reactant for reaction therein, an input unit inputting the reactant into the main body, and a filter unit installed in the main body to filter a precursor of the precursor generated by reacting with the reactant in the main body and a reaction solution.

Abstract: A co-precipitation reactor with a continuous filtering system mounted, wherein the co-precipitation reactor includes a main body accommodating a reactant for reaction therein, an input unit inputting the reactant into the main body, and a filter unit installed in the main body to filter a precursor of the precursor generated by reacting with the reactant in the main body and a reaction solution.

Abstract: Substrate heat treatment apparatus and method are provided. According to an embodiment of the present invention, there is provided a substrate heat treatment apparatus including an inner shell configured to form a substrate housing space to house at least one substrate, an outer shell configured to cover the inner shell, and having at least one gas hole, and at least one heater configured to heat the substrate, wherein the at least one gas hole is configured to allow a first gas to be injected into a space between the inner shell and the outer shell.

Abstract: Substrate heat treatment apparatus and method are provided. According to an embodiment of the present invention, there is provided a substrate heat treatment apparatus including an inner shell configured to form a substrate housing space to house at least one substrate, an outer shell configured to cover the inner shell, and having at least one gas hole, and at least one heater configured to heat the substrate, wherein the at least one gas hole is configured to allow a first gas to be injected into a space between the inner shell and the outer shell.

Abstract: A laser ablation apparatus. A target has a silicon region and an erbium region divided in a chamber with a silicon substrate opposite to the target. A target rotating axis rotates the target to alternately radiate laser light onto the silicon region and the erbium region, a laser generator irradiates laser light for generating a plume by ablating silicon from the silicon region and erbium from the erbium region outside the chamber.

Abstract: A method of manufacturing Er-doped silicon nano-dot arrays and a laser ablation apparatus are provided. In the method, a target having a silicon region and an erbium region is prepared. A silicon substrate is introduced opposite to the target. Laser light is irradiated onto the target, a plume containing silicon ablated from the silicon region and erbium ablated from the erbium region is generated, and an Er-doped silicon film is deposited on the silicon substrate from the plume. The Er-doped silicon film is patterned.

Abstract: The present invention relates to a method of manufacturing a nano transistor. The present invention manufactures the nano transistor without changing a conventional method of forming the nano transistor formed on a SOI substrate. Further, the present invention includes forming a N well and a P well at giving regions of an underlying silicon substrate so that a given voltage can be individually applied to a NMOS transistor and a PMOS transistor. Therefore, the present invention can control the threshold voltage to prevent an increase of the leakage current.

Abstract: The present invention relates to an ultra small size vertical MOSFET device having a vertical channel and a source/drain structure and a method for the manufacture thereof by using a silicon on insulator (SOI) substrate. To begin with, a first silicon conductive layer is formed by doping an impurity of a high concentration into a first single crystal silicon layer. Thereafter, a second single crystal silicon layer with the impurity of a low concentration and a second silicon conductive layer with the impurity of the high concentration are formed on the first silicon conductive layer. The second single crystal silicon layer and the second silicon conductive layer are vertically patterned into a predetermined configuration. Subsequently, a gate insulating layer is formed on entire surface.

Abstract: An ultra small-sized SOI MOSFET having a high integration density, low power consumption, but high performances, and a method of fabricating the same are provided.

Abstract: The present invention relates to a resistless dry lithography method and a method of forming a gate pattern using the same. The present invention utilizes the phenomena of altering the susceptibility to dry etching of a portion of Si layer exposed to the energetic electron beam. The dry lithography method comprises the steps of preparing a pattern-transferring object of silicon, exposing an electron beam to a desired portion of the pattern-transferring object, and performing reactive ion etch process to selectively etch the unexposed portion, thereby leaving the exposed portion of the pattern-transferring object. The present invention is an all-dry process and the entire lithography processes can be performed on one cluster equipment in a controlled environment, eliminating human handling of wafers and exposure to atmospheric environment to minimize contaminations during the process.

Abstract: An ultra small-sized SOI MOSFET having a high integration density, low power consumption, but high performances, and a method of fabricating the same are provided.

Abstract: Provided are a Schottky barrier tunnel transistor (SBTT) and a method of fabricating the same. The SBTT includes a buried oxide layer formed on a base substrate layer and having a groove at its upper surface; an ultra-thin silicon-on-insulator (SOI) layer formed across the groove; an insulating layer wrapping the SOI layer on the groove; a gate formed to be wider than the groove on the insulating layer; source and drain regions each positioned at both sides of the gate, the source and drain regions formed of silicide; and a conductive layer for filling the groove. In the SBTT, the SOI layer is formed to an ultra-thin thickness to minimize the occurrence of a leakage current, and a channel in the SOI layer below the gate is completely wrapped by the gate and the conductive layer, thereby improving the operational characteristics of the SBTT.

Abstract: Provided are a Schottky barrier tunnel transistor (SBTT) and a method of fabricating the same. The SBTT includes a buried oxide layer formed on a base substrate layer and having a groove at its upper surface; an ultra-thin silicon-on-insulator (SOI) layer formed across the groove; an insulating layer wrapping the SOI layer on the groove; a gate formed to be wider than the groove on the insulating layer; source and drain regions each positioned at both sides of the gate, the source and drain regions formed of silicide; and a conductive layer for filling the groove. In the SBTT, the SOI layer is formed to an ultra-thin thickness to minimize the occurrence of a leakage current, and a channel in the SOI layer below the gate is completely wrapped by the gate and the conductive layer, thereby improving the operational characteristics of the SBTT.

Abstract: The present invention relates to an ultra small size vertical MOSFET device having a vertical channel and a source/drain structure and a method for the manufacture thereof by using a silicon on insulator (SOI) substrate. To begin with, a first silicon conductive layer is formed by doping an impurity of a high concentration into a first single crystal silicon layer. Thereafter, a second single crystal silicon layer with the impurity of a low concentration and a second silicon conductive layer with the impurity of the high concentration are formed on the first silicon conductive layer. The second single crystal silicon layer and the second silicon conductive layer are vertically patterned into a predetermined configuration. Subsequently, a gate insulating layer is formed on entire surface.