Patents by Inventor Kyu Oh Lee

Kyu Oh Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180019219
    Abstract: A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad.
    Type: Application
    Filed: February 25, 2015
    Publication date: January 18, 2018
    Applicant: INTEL CORPORATION
    Inventors: Srinivas V. Pietambaram, Kyu Oh Lee
  • Patent number: 9865568
    Abstract: Disclosed herein are integrated circuit (IC) structures having recessed conductive contacts for package on package (PoP). For example, an IC structure may include: an IC package having a first resist surface; a recess disposed in the first resist surface, wherein a bottom of the recess includes a second resist surface; a first plurality of conductive contacts located at the first resist surface; and a second plurality of conductive contacts located at the second resist surface. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: January 9, 2018
    Assignee: Intel Corporation
    Inventors: Kyu-Oh Lee, Islam A. Salama, Ram S. Viswanath, Robert L. Sankman, Babak Sabi, Sri Chaitra Jyotsna Chavali
  • Publication number: 20170358528
    Abstract: Package substrates including conductive interconnects having noncircular cross-sections, and integrated circuit packages incorporating such package substrates, are described. In an example, a conductive pillar having a noncircular pillar cross-section is electrically connected to an escape line routing layer. The escape line routing layer may include several series of conductive pads having noncircular pad cross-sections. Accordingly, conductive traces, e.g., strip line escapes and microstrip escapes, may be routed between the series of conductive pads in a single escape line routing layer.
    Type: Application
    Filed: June 13, 2016
    Publication date: December 14, 2017
    Inventors: Kristof Kuwawi Darmawikarta, Kyu Oh Lee, Daniel Nicholas Sobieski
  • Patent number: 9837341
    Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes a combination of tin and zinc that mitigates precipitation of residual copper by promoting the formation of miconstituents in the microbump. In another embodiment, the microbump has a mass fraction of zinc, or a mass fraction of tin, that is different in various regions along a height of the microbump.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: December 5, 2017
    Assignee: Intel Corporation
    Inventors: Sri Chaitra J. Chavali, Amanda E. Schuckman, Kyu Oh Lee
  • Publication number: 20170318669
    Abstract: Some example forms relate to an electronic package. The electronic package includes a first dielectric layer that includes an electrical trace formed on a surface of the first dielectric layer and a second dielectric layer on the surface of the first dielectric layer. The second dielectric layer includes an opening. The electrical trace is within the opening. The electronic package includes an electrical interconnect that fills the opening and extends above an upper surface of the second dielectric layer such that the electrically interconnect is electrically connected to the electrical trace on the first dielectric layer.
    Type: Application
    Filed: July 14, 2017
    Publication date: November 2, 2017
    Inventors: Kristof Darmawikarta, Daniel Sobieski, Kyu Oh Lee, Sri Ranga Sai Boyapati
  • Patent number: 9791470
    Abstract: Magnet placement is described for integrated circuit packages. In one example, a terminal is applied to a magnet. The magnet is then placed on a top layer of a substrate with solder between the terminal and the top layer, and the solder is reflowed to attach the magnet to the substrate.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Feras Eid, Sasha N. Oster, Kyu Oh Lee, Sarah Haney
  • Publication number: 20170271264
    Abstract: Semiconductor packages with embedded bridge interconnects, and related assemblies and methods, are disclosed herein. In some embodiments, a semiconductor package may have a first side and a second side, and may include a bridge interconnect, embedded in a build-up material, having a first side with a plurality of conductive pads. The semiconductor package may also include a via having a first end that is narrower than a second end. The bridge interconnect and via may be arranged so that the first side of the semiconductor package is closer to the first side of the bridge interconnect than to the second side of the bridge interconnect, and so that the first side of the semiconductor package is closer to the first end of the via than to the second end of the via. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: September 19, 2014
    Publication date: September 21, 2017
    Inventor: Kyu-Oh LEE
  • Publication number: 20170207196
    Abstract: Disclosed herein are integrated circuit (IC) structures having recessed conductive contacts for package on package (PoP). For example, an IC structure may include: an IC package having a first resist surface; a recess disposed in the first resist surface, wherein a bottom of the recess includes a second resist surface; a first plurality of conductive contacts located at the first resist surface; and a second plurality of conductive contacts located at the second resist surface.
    Type: Application
    Filed: June 25, 2015
    Publication date: July 20, 2017
    Inventors: KYU-OH LEE, ISLAM A. SALAMA, RAM S. VISWANATH, ROBERT L. SANKMAN, BABAK SABI, SRI CHAITRA JYOTSNA CHAVALI
  • Publication number: 20170170109
    Abstract: Disclosed herein are integrated circuit (IC) structures having interposers with recesses. For example, an IC structure may include: an interposer having a resist surface; a recess disposed in the resist surface, wherein a bottom of the recess is surface-finished; and a plurality of conductive contacts located at the resist surface. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: June 25, 2015
    Publication date: June 15, 2017
    Inventors: KYU-OH LEE, ISLAM A. SALAMA
  • Publication number: 20170110422
    Abstract: A surface finish may be formed in a microelectronic structure, wherein the surface finish may include an interlayer comprising a refractory metal, phosphorus, and nickel, with the refractory metal having a content of between about 2 and 12% by weight and the phosphorus having a content of between about 2 and 12% by weight with the remainder being nickel. In one embodiment, the refractory metal of the interlayer may consist of one of tungsten, molybdenum, and ruthenium. In another embodiment, the interlayer may comprise the refractory metal being tungsten having a content of between about 5 and 6% by weight and phosphorus having a content of between about 5 and 6% by weight with the remainder being nickel.
    Type: Application
    Filed: October 14, 2015
    Publication date: April 20, 2017
    Applicant: INTEL CORPORATION
    Inventors: Srinivas V. Pietambaram, Kyu-Oh Lee
  • Publication number: 20170103941
    Abstract: Some embodiments of the present disclosure describe a multi-layer package with a bi-layered dielectric structure and associated techniques and configurations. In one embodiment, an integrated circuit (IC) package assembly includes a dielectric structure coupled with a metal layer, with the dielectric structure including a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has a thickness less than a thickness of the second dielectric layer and a dielectric loss tangent greater than a dielectric loss tangent of the second layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: May 13, 2015
    Publication date: April 13, 2017
    Inventors: Zheng Zhou, Mihir K. Roy, Chong Zhang, Kyu-Oh Lee, Amanda E. Schuckman
  • Patent number: 9607947
    Abstract: Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: March 28, 2017
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Nevin Altunyurt, Kyu Oh Lee, Krishna Bharath
  • Publication number: 20170064821
    Abstract: Some example forms relate to an electronic package. The electronic package includes a first dielectric layer that includes an electrical trace formed on a surface of the first dielectric layer and a second dielectric layer on the surface of the first dielectric layer. The second dielectric layer includes an opening. The electrical trace is within the opening. The electronic package includes an electrical interconnect that fills the opening and extends above an upper surface of the second dielectric layer such that the electrically interconnect is electrically connected to the electrical trace on the first dielectric layer.
    Type: Application
    Filed: August 31, 2015
    Publication date: March 2, 2017
    Inventors: Kristof Darmawikarta, Daniel Sobieski, Kyu Oh Lee, Sri Ranga Sai Boyapati
  • Patent number: 9505607
    Abstract: Methods of forming sensor integrated package devices and structures formed thereby are described. An embodiment includes providing a substrate core, wherein a first conductive trace structure and a second conductive trace structure are disposed on the substrate core, forming a cavity between the first conductive trace structure and the second conductive trace structure, and placing a magnet on a resist material disposed on a portion of each of the first and second conductive trace structures, wherein the resist material does not extend over the cavity.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: November 29, 2016
    Assignee: Intel Corporation
    Inventors: Kyu Oh Lee, Zheng Zhou, Islam A. Salama, Feras Eid, Sasha N. Oster, Lay Wai Kong, Javier Soto Gonzalez
  • Patent number: 9501068
    Abstract: A pressure sensor is integrated into an integrated circuit fabrication and packaging flow. In one example, a releasable layer is formed over a removable core. A first dielectric layer is formed. A metal layer is patterned to form conductive metal paths and to form a diaphragm with the metal. A second dielectric layer is formed over the metal layer and the diaphragm. A second metal layer is formed to connect with formed vias and to form a metal mesh layer over the diaphragm. The first dielectric layer is etched under the diaphragm to form a cavity and the cavity is covered to form a chamber adjoining the diaphragm.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: November 22, 2016
    Assignee: Intel Corporation
    Inventors: Kyu Oh Lee, Sasha N. Oster, Feras Eid, Sarah Haney
  • Publication number: 20160300796
    Abstract: Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.
    Type: Application
    Filed: June 15, 2016
    Publication date: October 13, 2016
    Inventors: Omkar G. Karhade, Nevin Altunyurt, Kyu Oh Lee, Krishna Bharath
  • Publication number: 20160280535
    Abstract: Methods of forming sensor integrated package devices and structures formed thereby are described. An embodiment includes providing a substrate core, wherein a first conductive trace structure and a second conductive trace structure are disposed on the substrate core, forming a cavity between the first conductive trace structure and the second conductive trace structure, and placing a magnet on a resist material disposed on a portion of each of the first and second conductive trace structures, wherein the resist material does not extend over the cavity.
    Type: Application
    Filed: March 27, 2015
    Publication date: September 29, 2016
    Applicant: Intel Corporation
    Inventors: Kyu Oh Lee, Zheng Zhou, Islam A. Salama, Feras Eid, Sasha N. Oster, Lay Wai Kong, Javier Soto Gonzalez
  • Patent number: 9391025
    Abstract: Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: July 12, 2016
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Nevin Altunyurt, Kyu Oh Lee, Krishna Bharath
  • Publication number: 20160161957
    Abstract: A pressure sensor is integrated into an integrated circuit fabrication and packaging flow. In one example, a releasable layer is formed over a removable core. A first dielectric layer is formed. A metal layer is patterned to form conductive metal paths and to form a diaphragm with the metal. A second dielectric layer is formed over the metal layer and the diaphragm. A second metal layer is formed to connect with formed vias and to form a metal mesh layer over the diaphragm. The first dielectric layer is etched under the diaphragm to form a cavity and the cavity is covered to form a chamber adjoining the diaphragm.
    Type: Application
    Filed: February 9, 2016
    Publication date: June 9, 2016
    Applicant: INTEL CORPORATION
    Inventors: KYU OH LEE, SASHA N. OSTER, FERAS EID, SARAH HANEY
  • Patent number: 9355952
    Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: May 31, 2016
    Assignee: Intel Corporation
    Inventors: Mark S. Hlad, Islam A. Salama, Mihir K. Roy, Tao Wu, Yueli Liu, Kyu Oh Lee