Patents by Inventor Kyu Oh Lee

Kyu Oh Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150037088
    Abstract: A lead-free solder alloy capable of forming solder joints in which electromigration and an increase in resistance during electric conduction at a high current density are suppressed has an alloy composition consisting essentially of 1.0-13.0 mass % of In, 0.1-4.0 mass % of Ag, 0.3-1.0 mass % of Cu, a remainder of Sn. The solder alloy has excellent tensile properties even at a high temperature exceeding 100° C. and can be used not only for CPUs but also for power semiconductors.
    Type: Application
    Filed: August 5, 2013
    Publication date: February 5, 2015
    Applicant: Senju Metal Industry Co., Ltd.
    Inventors: Tsukasa Ohnishi, Shunsaku Yoshikawa, Ken Tachibana, Yoshie Yamanaka, Hikaru Nomura, Kyu-oh Lee
  • Publication number: 20150008578
    Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.
    Type: Application
    Filed: September 9, 2014
    Publication date: January 8, 2015
    Inventors: Mark S. Hlad, Islam A. Salama, Mihir K. Roy, Tao Wu, Yueli Liu, Kyu Oh Lee
  • Publication number: 20150001733
    Abstract: Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Omkar G. Karhade, Nevin Altunyurt, Kyu Oh Lee, Krishna Bharath
  • Patent number: 8835217
    Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: September 16, 2014
    Assignee: Intel Corporation
    Inventors: Mark S Hlad, Islam A Salama, Mihir K Roy, Tao Wu, Yueli Liu, Kyu Oh Lee
  • Publication number: 20120161330
    Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Applicant: Intel Corporation
    Inventors: Mark S. Hlad, Islam A. Salama, Mihir K. Roy, Tao Wu, Yueli Liu, Kyu Oh Lee