Patents by Inventor Kyu Oh Lee

Kyu Oh Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150355035
    Abstract: This disclosure relates generally to an electronic assembly and methods that include a dielectric material forming a cavity, a magnet positioned to induce a magnetic field within the cavity, a conductive trace positioned, at least in part, within the cavity, and a frequency detection circuit configured to detect the frequency of the maximal electromotive force as induced and produce an output proportional to a temperature of the conductive trace.
    Type: Application
    Filed: June 5, 2014
    Publication date: December 10, 2015
    Inventors: Feras Eid, Sasha Oster, Sarah Haney, Kyu Oh Lee
  • Publication number: 20150318238
    Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.
    Type: Application
    Filed: July 13, 2015
    Publication date: November 5, 2015
    Inventors: Mark S. HLAD, Islam A. SALAMA, Mihir K. ROY, Tao WU, Yueli LIU, Kyu Oh LEE
  • Publication number: 20150228583
    Abstract: Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.
    Type: Application
    Filed: April 21, 2015
    Publication date: August 13, 2015
    Inventors: Omkar G. Karhade, Nevin Altunyurt, Kyu Oh Lee, Krishna Bharath
  • Patent number: 9093313
    Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: July 28, 2015
    Assignee: Intel Corporation
    Inventors: Mark S. Hlad, Islam A. Salama, Mihir K. Roy, Tao Wu, Yueli Liu, Kyu Oh Lee
  • Publication number: 20150183635
    Abstract: The integration of pressure or inertial sensors into an integrated circuit fabrication and packaging flow is described. In one example, a diaphragm is formed by depositing a metal over a first dielectric layer. A second dielectric layer is formed over the diaphragm. A metal mesh layer is formed over the second dielectric. The first dielectric layer is etched under the diaphragm to form a cavity. The cavity is lined with a sealing layer. The cavity is covered to form a chamber adjoining the diaphragm, and the cover is sealed against the cavity.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 2, 2015
    Inventors: Kyu Oh Lee, Sasha N. OSTER, Feras EID, Sarah HANEY
  • Publication number: 20150185247
    Abstract: Magnet placement is described for integrated circuit packages. In one example, a terminal is applied to a magnet. The magnet is then placed on a top layer of a substrate with solder between the terminal and the top layer, and the solder is reflowed to attach the magnet to the substrate.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 2, 2015
    Inventors: Feras Eid, Sasha N. OSTER, Kyu Oh LEE, Sarah HANEY
  • Patent number: 9041205
    Abstract: A semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: May 26, 2015
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Nevin Altunyurt, Kyu Oh Lee, Krishna Bharath
  • Publication number: 20150037087
    Abstract: A lead-free solder alloy consisting essentially of, in mass percent, Bi: 31-59%, Sb: 0.15-0.75%, at least one element selected from Cu: 0.3-1.0% and P: 0.002-0.055%, and a balance of Sn has a low melting point for suppressing warping of a thin substrate during soldering. It can form solder joints with high reliability even when used for soldering to electrodes having a Ni coating which contains P, since the growth of a P-rich layer is suppressed so that the shear strength of the joints is improved and the alloy has a high ductility and a high tensile strength.
    Type: Application
    Filed: August 5, 2013
    Publication date: February 5, 2015
    Applicant: Senju Metal Industry Co., Ltd.
    Inventors: Ken Tachibana, Hikaru Nomura, Kyu-oh Lee
  • Publication number: 20150037088
    Abstract: A lead-free solder alloy capable of forming solder joints in which electromigration and an increase in resistance during electric conduction at a high current density are suppressed has an alloy composition consisting essentially of 1.0-13.0 mass % of In, 0.1-4.0 mass % of Ag, 0.3-1.0 mass % of Cu, a remainder of Sn. The solder alloy has excellent tensile properties even at a high temperature exceeding 100° C. and can be used not only for CPUs but also for power semiconductors.
    Type: Application
    Filed: August 5, 2013
    Publication date: February 5, 2015
    Applicant: Senju Metal Industry Co., Ltd.
    Inventors: Tsukasa Ohnishi, Shunsaku Yoshikawa, Ken Tachibana, Yoshie Yamanaka, Hikaru Nomura, Kyu-oh Lee
  • Publication number: 20150008578
    Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.
    Type: Application
    Filed: September 9, 2014
    Publication date: January 8, 2015
    Inventors: Mark S. Hlad, Islam A. Salama, Mihir K. Roy, Tao Wu, Yueli Liu, Kyu Oh Lee
  • Publication number: 20150001733
    Abstract: Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Omkar G. Karhade, Nevin Altunyurt, Kyu Oh Lee, Krishna Bharath
  • Patent number: 8835217
    Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: September 16, 2014
    Assignee: Intel Corporation
    Inventors: Mark S Hlad, Islam A Salama, Mihir K Roy, Tao Wu, Yueli Liu, Kyu Oh Lee
  • Publication number: 20120161330
    Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Applicant: Intel Corporation
    Inventors: Mark S. Hlad, Islam A. Salama, Mihir K. Roy, Tao Wu, Yueli Liu, Kyu Oh Lee