Abstract: Semiconductor packages with embedded bridge interconnects, and related assemblies and methods, are disclosed herein. In some embodiments, a semiconductor package may have a first side and a second side, and may include a bridge interconnect, embedded in a build-up material, having a first side with a plurality of conductive pads. The semiconductor package may also include a via having a first end that is narrower than a second end. The bridge interconnect and via may be arranged so that the first side of the semiconductor package is closer to the first side of the bridge interconnect than to the second side of the bridge interconnect, and so that the first side of the semiconductor package is closer to the first end of the via than to the second end of the via. Other embodiments may be disclosed and/or claimed.

Abstract: Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

Abstract: Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.

Abstract: An integrated circuit (IC) structure includes a first IC package (ICP), including a first resist surface provided with a first plurality of conductive contacts (CCs), a first recess including a second resist surface disposed at a bottom of the recess and having a second plurality of CCs, and a second recess, including a third resist surface disposed at a bottom of the recess and provided with a fourth plurality of CCs. The IC structure further includes an IC component with a first surface and a second surface, the second surface having a third plurality of CCs coupled to the second plurality of CCs of the first ICP. The IC structure further includes a second ICP having a first surface and a second surface, with one or more CCs located at the second surface and coupled to at least one of the first plurality of CCs of the first ICP.

Abstract: A method for forming a substrate structure for an electrical component includes placing an electrically insulating laminate on a substrate and applying hot pressure to the electrically insulating laminate by a heatable plate. An average temperature of a surface temperature distribution within a center area of the heatable plate is higher than 80° C. during applying the hot pressure. Further, an edge area of the heatable plate laterally surrounds the center area and a temperature of the heatable plate within the edge area decreases from the center area towards an edge of the heatable plate during applying the hot pressure. A temperature at a location located vertically above an edge of the substrate during applying the hot pressure is at least 5° C. lower than the average temperature of the surface temperature distribution within the center area.

Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes nickel and tin, wherein the nickel aids in mitigating an absorption of seed layer copper. In another embodiment, the microbump has a mass fraction of tin, or a mass fraction of nickel, that is different in various regions along a height of the microbump.

Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.

Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes a combination of tin and zinc that mitigates precipitation of residual copper by promoting the formation of miconstituents in the microbump. In another embodiment, the microbump has a mass fraction of zinc, or a mass fraction of tin, that is different in various regions along a height of the microbump.

Abstract: A substrate for an integrated circuit package, the substrate comprising a dielectric, at least one conductor plane within the dielectric, and a planar magnetic structure comprising an organic magnetic laminate embedded within the dielectric, wherein the planar magnetic structure is integrated within the at least one conductor plane.

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a resist layer disposed on a conductive layer. The semiconductor package also has a bump disposed on the conductive layer. The bump has a top surface and one or more sidewalls. The semiconductor package further includes a surface finish disposed on the top surface and the one or more sidewalls of the bump. The semiconductor package may have the surface finish surround the top surface and sidewalls of the bumps to protect the bumps from Galvanic corrosion. The surface finish may include a nickel-palladium-gold (NiPdAu) surface finish. The semiconductor package may also have a seed disposed on a top surface of the resist layer, and a dielectric disposed on the seed. The dielectric may surround the sidewalls of the bump. The semiconductor package may include the seed to be an electroless copper seed.

Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.

Abstract: Embodiments are generally directed to indium solder metallurgy to control electro-migration. An embodiment of an electronic device includes a die; and a package substrate, wherein the die is bonded to the package substrate by an interconnection. The interconnection includes multiple interconnects, and wherein the interconnection includes a solder. The solder for the interconnection includes a combination of tin (Sn), copper (Cu), and indium (In).

Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes nickel and tin, wherein the nickel aids in mitigating an absorption of seed layer copper. In another embodiment, the microbump has a mass fraction of tin, or a mass fraction of nickel, that is different in various regions along a height of the microbump.

Abstract: A lead-free solder alloy capable of forming solder joints in which electromigration and an increase in resistance during electric conduction at a high current density are suppressed has an alloy composition consisting essentially of 1.0-13.0 mass % of In, 0.1-4.0 mass % of Ag, 0.3-1.0 mass % of Cu, a remainder of Sn. The solder alloy has excellent tensile properties even at a high temperature exceeding 100° C. and can be used not only for CPUs but also for power semiconductors.

Abstract: Semiconductor packages with embedded bridge interconnects, and related assemblies and methods, are disclosed herein. In some embodiments, a semiconductor package may have a first side and a second side, and may include a bridge interconnect, embedded in a build-up material, having a first side with a plurality of conductive pads. The semiconductor package may also include a via having a first end that is narrower than a second end. The bridge interconnect and via may be arranged so that the first side of the semiconductor package is closer to the first side of the bridge interconnect than to the second side of the bridge interconnect, and so that the first side of the semiconductor package is closer to the first end of the via than to the second end of the via. Other embodiments may be disclosed and/or claimed.

Abstract: Semiconductor packages with embedded bridge interconnects, and related assemblies and methods, are disclosed herein. In some embodiments, a semiconductor package may have a first side and a second side, and may include a bridge interconnect, embedded in a build-up material, having a first side with a plurality of conductive pads. The semiconductor package may also include a via having a first end that is narrower than a second end. The bridge interconnect and via may be arranged so that the first side of the semiconductor package is closer to the first side of the bridge interconnect than to the second side of the bridge interconnect, and so that the first side of the semiconductor package is closer to the first end of the via than to the second end of the via. Other embodiments may be disclosed and/or claimed.

Abstract: A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad.

Abstract: A method for forming a substrate structure for an electrical component includes placing an electrically insulating laminate on a substrate and applying hot pressure to the electrically insulating laminate by a heatable plate. An average temperature of a surface temperature distribution within a center area of the heatable plate is higher than 80° C. during applying the hot pressure. Further, an edge area of the heatable plate laterally surrounds the center area and a temperature of the heatable plate within the edge area decreases from the center area towards an edge of the heatable plate during applying the hot pressure. A temperature at a location located vertically above an edge of the substrate during applying the hot pressure is at least 5° C. lower than the average temperature of the surface temperature distribution within the center area.

Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

Abstract: A lead-free solder alloy capable of forming solder joints in which electromigration and an increase in resistance during electric conduction at a high current density are suppressed has an alloy composition consisting essentially of 1.0-13.0 mass % of In, 0.1-4.0 mass % of Ag, 0.3-1.0 mass % of Cu, a remainder of Sn. The solder alloy has excellent tensile properties even at a high temperature exceeding 100° C. and can be used not only for CPUs but also for power semiconductors.