Patents by Inventor Kyu-Ho Cho
Kyu-Ho Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128502Abstract: An embodiment solid electrolyte includes a first compound and a second compound. The first compound is represented by a first chemical formula Li7-aPS6-a(X11-bX2b)a, wherein X1 and X2 are the same or different and each represents F, Cl, Br, or I, and wherein 0<a?2 and 0<b<1, and the second compound is represented by a second chemical formula Li7-cP1-2dMdS6-c-3d(X11-eX2e)c, wherein X1 and X2 are the same or different and each represents F, Cl, Br, or I, wherein M represents Ge, Si, Sn, or any combination thereof, and wherein 0<c?2, 0<d<0.5, and 0<e<1.Type: ApplicationFiled: August 14, 2023Publication date: April 18, 2024Inventors: Sa Heum Kim, Yong Jun Jang, Yong Gu Kim, Sung Man Cho, Sun Ho Choi, Seong Hyeon Choi, Kyu Sung Park, Young Gyoon Ryu, Suk Gi Hong, Pil Sang Yun, Myeong Ju Ha, Hyun Beom Kim, Hwi Chul Yang
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Patent number: 11929389Abstract: An integrated circuit device includes a lower electrode, an upper electrode, and a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure including a first surface facing the lower electrode and a second surface facing the upper electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a plurality of grains extending from the first surface to the second surface and a second dielectric layer including a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer in a level lower than the second surface. The second dielectric material includes a material having bandgap energy which is higher than bandgap energy of the first dielectric material.Type: GrantFiled: May 19, 2021Date of Patent: March 12, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Youn-soo Kim, Seung-min Ryu, Chang-su Woo, Hyung-suk Jung, Kyu-ho Cho, Youn-joung Cho
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Publication number: 20240071071Abstract: In an embodiment an apparatus includes a processor configured to generate a feature extraction module using a dataset in which an attribute for each object is defined, receive an image obtained by a camera, extract an attribute of an object of interest from the image using the learned feature extraction module, identify an object re-identification candidate group based on the extracted attribute of the object of interest and re-identify the object of interest based on the identified object re-identification candidate group.Type: ApplicationFiled: April 13, 2023Publication date: February 29, 2024Inventors: Hyeon Seok Jung, Kyung Hwan Cho, Moon Sub Jin, Kyu Sang Choi, Bum Sub Ham, Chan Ho Eom, Geon Lee
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Publication number: 20230307226Abstract: Disclosed is a method of depositing thin film, the method comprising: supplying an adduct precursor to the inside of a chamber in which a substrate including at least one gap feature is placed so that the adduct precursor is adsorbed to the substrate; purging the interior of the chamber; and supplying a reaction material to the inside of the chamber so that the reaction material reacts with the adduct precursor to form the thin film and fill the gap feature, wherein the adduct precursor is formed by mixing 1 to 5 moles of a compound and 1 to 5 moles of a metal compound.Type: ApplicationFiled: May 10, 2023Publication date: September 28, 2023Applicant: EGTM Co., Ltd.Inventors: Ha Na KIM, Ju Hwan ` JEONG, Kyu Ho CHO, Jae Min KIM, Duck Hyeon SEO, Ji Yeon HAN, Hyun Ju JUNG
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Publication number: 20230287014Abstract: Disclosed is a method for manufacturing an aluminum precursor formed by mixing 1 to 3 moles of a compound represented by the following Chemical Formula 1 or following Chemical Formula 2 and 1 to 3 moles of a compound represented by the following Chemical Formula 3. wherein X is O or S, and R1 or R2 is each independently selected from an alkyl group having 1 to 8 carbon atoms, a cycloalkyl group having 3 to 6 carbon atoms, and an aryl group having 6 to 12 carbon atoms. wherein X is O or S, n is 1 to 5, and R1 to R4 are each independently selected from a hydrogen atom, an alkyl group having 1 to 5 carbon atoms, a cycloalkyl group having 3 to 6 carbon atoms, and an aryl group having 6 to 12 carbon atoms. wherein R1, R2 and R3 are different from each other, and each independently selected from a hydrogen atom, an alkyl group having 1 to 6 carbon atoms, a dialkylamine having 1 to 6 carbon atoms, a cycloamine group having 1 to 6 carbon atoms, or a halogen atom.Type: ApplicationFiled: May 10, 2023Publication date: September 14, 2023Applicant: EGTM Co., Ltd.Inventors: Kyu Ho CHO, Ha Na KIM, Jae Min KIM, Ji Yeon HAN, Duck Hyeon SEO, Ju Hwan JEONG, Hyun Ju JUNG, Hyeon Sik CHO, Myeong Il KIM
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Patent number: 11705483Abstract: A capacitor includes a lower electrode including a first metal material and having a first crystal size in a range of a few nanometers, a dielectric layer covering the lower electrode and having a second crystal size that is a value of a crystal expansion ratio times the first crystal size and an upper electrode including a second metal material and covering the dielectric layer. The upper electrode has a third crystal size smaller than the second crystal size.Type: GrantFiled: July 2, 2021Date of Patent: July 18, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Sun Kim, Sang-Yeol Kang, Kyoo-Ho Jung, Kyu-Ho Cho, Hyo-Sik Mun
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Patent number: 11588012Abstract: A method of manufacturing a semiconductor device includes forming a preliminary lower electrode layer on a substrate, the preliminary lower electrode layer including a niobium oxide; converting at least a portion of the preliminary lower electrode layer to a first lower electrode layer comprising a niobium nitride by performing a nitridation process on the preliminary lower electrode layer; forming a dielectric layer on the first lower electrode layer; and forming an upper electrode on the dielectric layer.Type: GrantFiled: March 12, 2021Date of Patent: February 21, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-goo Kang, Sang-yeol Kang, Youn-soo Kim, Jin-su Lee, Hyung-suk Jung, Kyu-ho Cho
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Publication number: 20220336574Abstract: A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Sang Yeol KANG, Kyu Ho CHO, Han Jin LIM, Cheol Seong HWANG
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Patent number: 11411069Abstract: A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.Type: GrantFiled: September 24, 2020Date of Patent: August 9, 2022Assignees: Samsung Electronics Co., Ltd., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Sang Yeol Kang, Kyu Ho Cho, Han Jin Lim, Cheol Seong Hwang
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Patent number: 11233118Abstract: An integrated circuit (IC) device includes an electrode, a dielectric layer facing the electrode, and a plurality of interface layers interposed between the electrode and the dielectric layer and including a first metal. The plurality of interface layers includes a first interface layer and a second interface layer. An oxygen content of the first interface layer is different from an oxygen content of the second interface layer.Type: GrantFiled: May 1, 2019Date of Patent: January 25, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Lim Park, Sun-Min Moon, Chang-Hwa Jung, Young-Geun Park, Jong-Bom Seo, Kyu-Ho Cho
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Publication number: 20210343832Abstract: A capacitor includes a lower electrode including a first metal material and having a first crystal size in a range of a few nanometers, a dielectric layer covering the lower electrode and having a second crystal size that is a value of a crystal expansion ratio times the first crystal size and an upper electrode including a second metal material and covering the dielectric layer. The upper electrode has a third crystal size smaller than the second crystal size.Type: ApplicationFiled: July 2, 2021Publication date: November 4, 2021Inventors: EUN-SUN KIM, SANG-YEOL KANG, KYOO-HO JUNG, KYU-HO CHO, HYO-SIK MUN
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Publication number: 20210273039Abstract: An integrated circuit device includes a lower electrode, an upper electrode, and a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure including a first surface facing the lower electrode and a second surface facing the upper electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a plurality of grains extending from the first surface to the second surface and a second dielectric layer including a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer in a level lower than the second surface. The second dielectric material includes a material having bandgap energy which is higher than bandgap energy of the first dielectric material.Type: ApplicationFiled: May 19, 2021Publication date: September 2, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Youn-soo KIM, Seung-min RYU, Chang-su WOO, Hyung-suk JUNG, Kyu-ho CHO, Youn-joung CHO
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Patent number: 11088240Abstract: A capacitor includes a lower electrode including a first metal material and having a first crystal size in a range of a few nanometers, a dielectric layer covering the lower electrode and having a second crystal size that is a value of a crystal expansion ratio times the first crystal size and an upper electrode including a second metal material and covering the dielectric layer. The upper electrode has a third crystal size smaller than the second crystal size.Type: GrantFiled: June 18, 2019Date of Patent: August 10, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Sun Kim, Sang-Yeol Kang, Kyoo-Ho Jung, Kyu-Ho Cho, Hyo-Sik Mun
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Publication number: 20210202693Abstract: A method of manufacturing a semiconductor device includes forming a preliminary lower electrode layer on a substrate, the preliminary lower electrode layer including a niobium oxide; converting at least a portion of the preliminary lower electrode layer to a first lower electrode layer comprising a niobium nitride by performing a nitridation process on the preliminary lower electrode layer; forming a dielectric layer on the first lower electrode layer; and forming an upper electrode on the dielectric layer.Type: ApplicationFiled: March 12, 2021Publication date: July 1, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Jun-goo KANG, Sang-yeol KANG, Youn-soo KIM, Jin-su LEE, Hyung-suk JUNG, Kyu-ho CHO
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Patent number: 11043553Abstract: An integrated circuit device includes a lower electrode, an upper electrode, and a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure including a first surface facing the lower electrode and a second surface facing the upper electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a plurality of grains extending from the first surface to the second surface and a second dielectric layer including a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer in a level lower than the second surface. The second dielectric material includes a material having bandgap energy which is higher than bandgap energy of the first dielectric material.Type: GrantFiled: July 24, 2019Date of Patent: June 22, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Youn-soo Kim, Seung-min Ryu, Chang-su Woo, Hyung-suk Jung, Kyu-ho Cho, Youn-joung Cho
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Patent number: 10978552Abstract: A method of manufacturing a semiconductor device includes forming a preliminary lower electrode layer on a substrate, the preliminary lower electrode layer including a niobium oxide; converting at least a portion of the preliminary lower electrode layer to a first lower electrode layer comprising a niobium nitride by performing a nitridation process on the preliminary lower electrode layer; forming a dielectric layer on the first lower electrode layer; and forming an upper electrode on the dielectric layer.Type: GrantFiled: February 12, 2019Date of Patent: April 13, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun-goo Kang, Sang-yeol Kang, Youn-soo Kim, Jin-su Lee, Hyung-suk Jung, Kyu-ho Cho
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Publication number: 20210020735Abstract: A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.Type: ApplicationFiled: September 24, 2020Publication date: January 21, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Sang Yeol KANG, Kyu Ho CHO, Han Jin LIM, Cheol Seong HWANG
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Patent number: 10825893Abstract: A semiconductor device includes a first electrode on a substrate, a second electrode on the substrate, a dielectric layer structure between the first electrode and the second electrode, and a crystallization inducing layer between the dielectric layer structure and the first electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a second dielectric layer on the first dielectric layer and including a second dielectric material.Type: GrantFiled: June 8, 2018Date of Patent: November 3, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Kyu-ho Cho, Sang-yeol Kang, Sun-min Moon, Young-lim Park, Jong-bom Seo
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Patent number: 10825889Abstract: A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.Type: GrantFiled: June 20, 2018Date of Patent: November 3, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sang Yeol Kang, Kyu Ho Cho, Han Jin Lim, Cheol Seong Hwang
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Publication number: 20200127079Abstract: A capacitor includes a lower electrode including a first metal material and having a first crystal size in a range of a few nanometers, a dielectric layer covering the lower electrode and having a second crystal size that is a value of a crystal expansion ratio times the first crystal size and an upper electrode including a second metal material and covering the dielectric layer. The upper electrode has a third crystal size smaller than the second crystal size.Type: ApplicationFiled: June 18, 2019Publication date: April 23, 2020Inventors: EUN-SUN KIM, SANG-YEOL KANG, KYOO-HO JUNG, KYU-HO CHO, HYO-SIK MUN