Abstract: A package circuit board having a reduced package size. The package circuit board may include a semiconductor substrate in place of a printed circuit board. The package circuit board may further include a microelectronic chip mounted on the semiconductor substrate, the microelectronic chip having at least one of active and passive elements formed on the semiconductor substrate semiconductor substrate.

Abstract: A package circuit board having a reduced package size. The package circuit board may include a semiconductor substrate in place of a printed circuit board. The package circuit board may further include a microelectronic chip mounted on the semiconductor substrate, the microelectronic chip having at least one of active and passive elements formed on the semiconductor substrate semiconductor substrate.

Abstract: A semiconductor package on package includes a tower package, an upper package stacked over the lower package, a plug wire combined to any one of an upper portion of the tower package and a lower portion of the upper package, and a socket wire combined to any one of the upper portion of the lower package and the lower portion of the upper package. The plug wire is plugged into the socket wire to electrically connect the upper and lower packages.

Abstract: In a bonding configuration for a semiconductor device package, the bonding angles of the bonding wires are maintained within acceptable limits, without causing an increase in the chip die size, and without necessitating the use of the corner rule. In this manner, the occurrence of shorting between adjacent bonding wires can be mitigated or eliminated, and device net die count during fabrication can be increased.

Abstract: A semiconductor package on package includes a tower package, an upper package stacked over the lower package, a plug wire combined to any one of an upper portion of the tower package and a lower portion of the upper package, and a socket wire combined to any one of the upper portion of the lower package and the lower portion of the upper package. The plug wire is plugged into the socket wire to electrically connect the upper and lower packages.

Abstract: The present invention relates to a semiconductor package having a conductive molding compound to prevent static charge accumulation. By using a conductive molding compound heat conductivity is also increased and heat generated by the semiconductor chip is more effectively dissipated externally. Additionally, the conductive compound blocks electromagnetic waves making possible an optimal semiconductor package satisfying the electromagnetic compatibility (EMC) and increasing the reliability of the semiconductor chip especially when processing high-speed signals.

Abstract: A semiconductor chip package may include a substrate, which may have bonding pads formed thereon. A semiconductor chip mounted on the substrate may have chip pads, and electrical connections for connecting the chip pads of the semiconductor chip to the substrate bonding pads. The semiconductor chip and the electrical connections on the substrate may be encapsulated, and a board attached to a portion of a surface of the substrate may not be encapsulated.

Abstract: A printed circuit board for a high-speed semiconductor package uses bonding wires as a shield structure, e.g., to shield an open portion of signal transmission lines, and thereby reduce the likelihood of coupling noises, e.g., between signal transmission lines.

Abstract: Provided is a semiconductor device package in which instability of a bonding wire that may occur when a plurality of semiconductor chips are stacked is prevented and which obtains a light, thin and small structure. The semiconductor device package includes a substrate having a plurality of substrate pads on a top surface of the semiconductor device package and includes a plurality of semiconductor chips stacked on the substrate. Each of the semiconductor chips have a chip pad electrically connected to a common pin, e.g., to which a common signal may be concurrently applied to each of the semiconductor chips. An interposer chip, also stacked on the substrate, has a connecting wire electrically connected to the chip pad, the common pin of each of the semiconductor chips being thereby electrically coupled at the connecting wire via the chip pad, and the connecting wire being thereby electrically connected to the substrate pad.

Abstract: Provided is a semiconductor device package in which instability of a bonding wire that may occur when a plurality of semiconductor chips are stacked is prevented and which obtains a light, thin and small structure. The semiconductor device package includes a substrate having a plurality of substrate pads on a top surface of the semiconductor device package and includes a plurality of semiconductor chips stacked on the substrate. Each of the semiconductor chips have a chip pad electrically connected to a common pin, e.g., to which a common signal may be concurrently applied to each of the semiconductor chips. An interposer chip, also stacked on the substrate, has a connecting wire electrically connected to the chip pad, the common pin of each of the semiconductor chips being thereby electrically coupled at the connecting wire via the chip pad, and the connecting wire being thereby electrically connected to the substrate pad.

Abstract: A printed circuit board for a high-speed semiconductor package uses bonding wires as a shield structure, e.g., to shield an open portion of signal transmission lines, and thereby reduce the likelihood of coupling noises, e.g., between signal transmission lines.

Abstract: The present invention relates to a semiconductor package having a conductive molding compound to prevent static charge accumulation. By using a conductive molding compound heat conductivity is also increased and heat generated by the semiconductor chip is more effectively dissipated externally. Additionally, the conductive compound blocks electromagnetic waves making possible an optimal semiconductor package satisfying the electromagnetic compatibility (EMC) and increasing the reliability of the semiconductor chip especially when processing high-speed signals.

Abstract: In one embodiment, a semiconductor package comprises a base frame and a lower semiconductor chip electrically coupled to the base frame. The lower semiconductor chip has a first bond pad formed on a top surface thereof. The package further includes an upper semiconductor chip overlying the lower semiconductor chip. The upper semiconductor chip has a third bond pad formed on a bottom surface thereof. The package comprises a first conductive bump and a second conductive bump jointly coupling the first bond pad to the third bond pad.

Abstract: A semiconductor chip package may include a substrate, which may have bonding pads formed thereon. A semiconductor chip mounted on the substrate may have chip pads, and electrical connections for connecting the chip pads of the semiconductor chip to the substrate bonding pads. The semiconductor chip and the electrical connections on the substrate may be encapsulated, and a board attached to a portion of a surface of the substrate may not be encapsulated.

Abstract: A package circuit board having a reduced package size. The package circuit board may include a semiconductor substrate in place of a printed circuit board. The package circuit board may further include a microelectronic chip mounted on the semiconductor substrate, the microelectronic chip having at least one of active and passive elements formed on the semiconductor substrate semiconductor substrate.