Patents by Inventor Lai Guan Tang

Lai Guan Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210303491
    Abstract: Systems or methods of the present disclosure may provide high-bandwidth, low-latency connectivity for inter-die and/or intra-die communication of a modularized integrated circuit system. Such an integrated circuit system may include a first die of fabric circuitry sector(s), a second die of modular periphery intellectual property (IP), a passive silicon interposer coupling the first die to the second die, and a modular interface that includes a network-on-chip (NOC). The modular interface may provide high-bandwidth, low-latency communication between the first die and the second, between the fabric circuitry sector(s), and between the first die and a third die.
    Type: Application
    Filed: June 14, 2021
    Publication date: September 30, 2021
    Inventors: George Chong Hean Ooi, Lai Guan Tang, Chee Hak Teh
  • Patent number: 11128301
    Abstract: Systems and methods related to multi-die integrated circuits that may include dies having high-speed core interconnects. The high-speed core interconnects may be used to directly connect two adjacent dies.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: September 21, 2021
    Assignee: Intel Corporation
    Inventors: Lai Guan Tang, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Patent number: 11080449
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, MD Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
  • Patent number: 11062070
    Abstract: Systems or methods of the present disclosure may facilitate meeting connectivity demands between the dies of the modularized integrated circuits. Such an integrated circuit system may include a first die of programmable fabric circuitry that is communicatively coupled to a second die of modular periphery intellectual property (IP) tile via a modular interface. The modular interface may enable communication between a first microbump of the first die and a second microbump of the second die using a time-division multiplexing (TDM) technique. The modular interface may also enable communication between the first microbump and the second microbump using a wire-to-wire connection that does not comprise the TDM technique.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Lai Guan Tang, Chee Hak Teh
  • Patent number: 11036660
    Abstract: Systems or methods of the present disclosure may provide high-bandwidth, low-latency connectivity for inter-die and/or intra-die communication of a modularized integrated circuit system. Such an integrated circuit system may include a first die of fabric circuitry sector(s), a second die of modular periphery intellectual property (IP), a passive silicon interposer coupling the first die to the second die, and a modular interface that includes a network-on-chip (NOC). The modular interface may provide high-bandwidth, low-latency communication between the first die and the second, between the fabric circuitry sector(s), and between the first die and a third die.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 15, 2021
    Assignee: Intel Corporation
    Inventors: George Chong Hean Ooi, Lai Guan Tang, Chee Hak Teh
  • Publication number: 20210111116
    Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.
    Type: Application
    Filed: December 22, 2020
    Publication date: April 15, 2021
    Inventors: Chee Hak Teh, Chee Seng Leong, Lai Guan Tang, Han Wooi Lim, Hee Kong Phoon
  • Patent number: 10886218
    Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Chee Hak Teh, Chee Seng Leong, Lai Guan Tang, Han Wooi Lim, Hee Kong Phoon
  • Publication number: 20200321964
    Abstract: Systems and methods related to multi-die integrated circuits that may include dies having high-speed core interconnects. The high-speed core interconnects may be used to directly connect two adjacent dies.
    Type: Application
    Filed: May 22, 2020
    Publication date: October 8, 2020
    Inventors: Lai Guan Tang, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Publication number: 20200226313
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, MD Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
  • Patent number: 10666261
    Abstract: Systems and methods related to multi-die integrated circuits that may include dies having high-speed core interconnects. The high-speed core interconnects may be used to directly connect two adjacent dies.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Lai Guan Tang, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Patent number: 10642946
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, Md Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
  • Publication number: 20200133902
    Abstract: Systems and method include one or more die coupled to an interposer. The interposer includes interconnection circuitry configured to electrically connect the one or more die together via the interposer. The interposer also includes translation circuitry configured to translate communications as they pass through the interposer. For instance, in the interposer, the translation circuitry translates communications, in the interposer, from a first protocol of a first die of the one or more die to a second protocol of a second die of the one or more die.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 30, 2020
    Inventors: Lai Guan Tang, Ankireddy Nalamalpu, Dheeraj Subbareddy, Chee Hak Teh, MD Altaf Hossain
  • Publication number: 20190326210
    Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 24, 2019
    Inventors: Chee Hak Teh, Chee Seng Leong, Lai Guan Tang, Han Wooi Lim, Hee Kong Phoon
  • Patent number: 10382013
    Abstract: Systems, methods, and devices for voltage identification using a pulse-width modulation signal are provided. Such an integrated circuit device may include an input/output (I/O) interface and voltage identification (VID) circuitry. The VID circuitry may be coupled to the input/output interface. The voltage identification circuitry may generate a voltage identification signal that is output on the input/output interface. The voltage identification signal may include a pulsed signal having a particular duty cycle that corresponds to a specified voltage level to enable a voltage regulator that receives the voltage identification signal to provide an input voltage to the integrated circuit device at the specified voltage level.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: August 13, 2019
    Assignee: Altera Corporation
    Inventors: Lai Guan Tang, Kris Dehnel, Benoit Herve
  • Publication number: 20190227963
    Abstract: Systems or methods of the present disclosure may provide high-bandwidth, low-latency connectivity for inter-die and/or intra-die communication of a modularized integrated circuit system. Such an integrated circuit system may include a first die of fabric circuitry sector(s), a second die of modular periphery intellectual property (IP), a passive silicon interposer coupling the first die to the second die, and a modular interface that includes a network-on-chip (NOC). The modular interface may provide high-bandwidth, low-latency communication between the first die and the second, between the fabric circuitry sector(s), and between the first die and a third die.
    Type: Application
    Filed: March 28, 2019
    Publication date: July 25, 2019
    Inventors: George Chong Hean Ooi, Lai Guan Tang, Chee Hak Teh
  • Publication number: 20190227590
    Abstract: A circuit system includes an interposer that has a first clock network and first and second integrated circuit dies that are mounted on the interposer. The first integrated circuit die includes a phase detector circuit, an adjustable delay circuit that generates a second clock signal in response to a first clock signal received from the first clock network, and a second clock network that generates a third clock signal in response to the second clock signal. The second integrated circuit die comprises a third clock network that generates a fourth clock signal in response to the first clock signal received from the first clock network. The phase detector circuit controls a delay provided by the adjustable delay circuit to the second clock signal based on a phase comparison between phases of the third and fourth clock signals.
    Type: Application
    Filed: March 28, 2019
    Publication date: July 25, 2019
    Applicant: Intel Corporation
    Inventors: Jeffrey Chromczak, Chooi Pei Lim, Lai Guan Tang, Chee Hak Teh, MD Altaf Hossain, Dheeraj Subbareddy, Ankireddy Nalamalpu
  • Publication number: 20190220566
    Abstract: Systems or methods of the present disclosure may facilitate meeting connectivity demands between the dies of the modularized integrated circuits. Such an integrated circuit system may include a first die of programmable fabric circuitry that is communicatively coupled to a second die of modular periphery intellectual property (IP) tile via a modular interface. The modular interface may enable communication between a first microbump of the first die and a second microbump of the second die using a time-division multiplexing (TDM) technique. The modular interface may also enable communication between the first microbump and the second microbump using a wire-to-wire connection that does not comprise the TDM technique.
    Type: Application
    Filed: March 28, 2019
    Publication date: July 18, 2019
    Inventors: Lai Guan Tang, Chee Hak Teh
  • Publication number: 20190158096
    Abstract: A method includes detecting an open in a first IO element of a first bank of IOs and not in a second bank of IOs. The first and second banks of IOs are in a channel of a first die. The method includes shifting a first connection between the first IO element and a first core fabric of the first die to second connection between a second IO element and the first core fabric. The second IO element is in the first bank of IOs. The method includes shifting a third connection between a third IO element and a second core fabric of a second die to fourth connection between a fourth IO element and the second core fabric. The third and fourth IO elements are in a third bank of IOs of the second die. The method includes not shifting connections in the second and fourth banks of IOs.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 23, 2019
    Applicant: Intel Corporation
    Inventors: Lai Guan Tang, Hup Chin Teh, Kiun Kiet Jong
  • Publication number: 20190140649
    Abstract: Systems and methods related to multi-die integrated circuits that may include dies having high-speed core interconnects. The high-speed core interconnects may be used to directly connect two adjacent dies.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Lai Guan Tang, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Publication number: 20190138680
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, MD Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang