Patents by Inventor Lai Guan Tang

Lai Guan Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10211833
    Abstract: An integrated circuit includes a circuit block, a storage circuit that stores a static power gating control signal, a logic gate circuit that receives a dynamic power gating control signal and the static power gating control signal from the storage circuit, and a transistor coupled between the circuit block and a supply node at a supply voltage. A conductive state of the transistor is determined by an output signal of the logic gate circuit. The transistor is turned off to provide power gating to the circuit block in response to a change in the output signal of the logic gate circuit that is caused by the static power gating control signal or by the dynamic power gating control signal.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: February 19, 2019
    Assignee: Altera Corporation
    Inventor: Lai Guan Tang
  • Publication number: 20190044520
    Abstract: An IC, operable at a first clock phase, includes first and second IOs and a PLL. The PLL includes a control circuit, an input to receive a first clock signal, an output to output a second clock signal, and a first detector to generate a first phase difference signal from the first and second clock signals. The IC includes a second phase detector that is coupled to the PLL's output to receive the second clock signal and is coupled to the first IO to receive a third clock single from a second IC, which is operable at a second clock phase. The second detector generates a second phase difference signal from the second and third clock signals. If the PLL uses the second phase difference signal to generate the second clock signal, then the second clock signal is synchronized with the third clock signal for synchronous data transfer.
    Type: Application
    Filed: June 29, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Lai Guan Tang, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Patent number: 10177753
    Abstract: An integrated circuit includes a control circuit, a first-in first-out circuit, and a serializer circuit. The control circuit generates parallel pulse-width modulation data in first parallel pulse-width modulation signals. The first-in first-out circuit stores the parallel pulse-width modulation data indicated by the first parallel pulse-width modulation signals. The first-in first-out circuit outputs the stored parallel pulse-width modulation data in second parallel pulse-width modulation signals. The serializer circuit converts the parallel pulse-width modulation data indicated by the second parallel pulse-width modulation signals to serial pulse-width modulation data in a serial pulse-width modulation signal.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: January 8, 2019
    Assignee: Altera Corporation
    Inventors: Lai Guan Tang, Kang Syn Ting
  • Publication number: 20180083626
    Abstract: An integrated circuit includes a circuit block, a storage circuit that stores a static power gating control signal, a logic gate circuit that receives a dynamic power gating control signal and the static power gating control signal from the storage circuit, and a transistor coupled between the circuit block and a supply node at a supply voltage. A conductive state of the transistor is determined by an output signal of the logic gate circuit. The transistor is turned off to provide power gating to the circuit block in response to a change in the output signal of the logic gate circuit that is caused by the static power gating control signal or by the dynamic power gating control signal.
    Type: Application
    Filed: September 20, 2016
    Publication date: March 22, 2018
    Applicant: Altera Corporation
    Inventor: Lai Guan Tang
  • Publication number: 20180041201
    Abstract: An integrated circuit includes a control circuit, a first-in first-out circuit, and a serializer circuit. The control circuit generates parallel pulse-width modulation data in first parallel pulse-width modulation signals. The first-in first-out circuit stores the parallel pulse-width modulation data indicated by the first parallel pulse-width modulation signals. The first-in first-out circuit outputs the stored parallel pulse-width modulation data in second parallel pulse-width modulation signals. The serializer circuit converts the parallel pulse-width modulation data indicated by the second parallel pulse-width modulation signals to serial pulse-width modulation data in a serial pulse-width modulation signal.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Applicant: Altera Corporation
    Inventors: Lai Guan Tang, Kang Syn Ting
  • Publication number: 20170288648
    Abstract: Systems, methods, and devices for voltage identification using a pulse-width modulation signal are provided. Such an integrated circuit device may include an input/output (I/O) interface and voltage identification (VID) circuitry. The VID circuitry may be coupled to the input/output interface. The voltage identification circuitry may generate a voltage identification signal that is output on the input/output interface. The voltage identification signal may include a pulsed signal having a particular duty cycle that corresponds to a specified voltage level to enable a voltage regulator that receives the voltage identification signal to provide an input voltage to the integrated circuit device at the specified voltage level.
    Type: Application
    Filed: March 31, 2016
    Publication date: October 5, 2017
    Inventors: Lai Guan Tang, Kris Dehnel, Benoit Herve
  • Patent number: 8780121
    Abstract: An example of a controller circuit may include a policy module to generate a power reduction policy output based on a processor power state input. The power reduction policy output may also be generated based on a graphics render engine idleness input. The circuit can also include a clock masking cell to apply a clock masking configuration to a graphics render clock trunk based on the power reduction policy output.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: July 15, 2014
    Assignee: Intel Corporation
    Inventors: Lai Kuan Chong, Lai Guan Tang
  • Publication number: 20110148887
    Abstract: An example of a controller circuit may include a policy module to generate a power reduction policy output based on a processor power state input. The power reduction policy output may also be generated based on a graphics render engine idleness input. The circuit can also include a clock masking cell to apply a clock masking configuration to a graphics render clock trunk based on the power reduction policy output.
    Type: Application
    Filed: October 20, 2010
    Publication date: June 23, 2011
    Inventors: Lai Kuan Chong, Lai Guan Tang