Abstract: Certain aspects of the present disclosure provide methods and apparatus for processing signals using a current-mode biquad filter, which may have a tunable bias current and/or tunable capacitance. One example apparatus is a current-mode biquad filter circuit that includes a first input current node, a first capacitive element coupled to the first input current node, a first output current node, a first active filter circuit coupled between the first input current node and the first output current node, and a second active filter circuit coupled between the first input current node and the first output current node. The second active filter circuit is complementary to the first active filter circuit.

Abstract: In certain aspects, a receiver includes first amplifiers, wherein each one of the first amplifiers comprises an input and an output. The receiver also includes second amplifiers, wherein each one of the second amplifiers comprises an input and an output, and the outputs of the second amplifiers are coupled to a combining node. The receiver also includes transmission lines, wherein each one of the transmission lines is coupled between the output of a respective one of the first amplifiers and the input of a respective one of the second amplifiers. The receiver further includes a load coupled to the combining node, and receiver elements, wherein each one of the receiver elements comprises an input and an output, and the output of each one of the receiver elements is coupled to the input of a respective one of the first amplifiers.

Abstract: A frequency synthesizer system may include a first voltage-controlled oscillator (VCO) circuit, a second VCO circuit, and multiplexing circuitry. The multiplexing circuitry may be configured to select either the output of the first VCO circuit or the output of the second VCO circuit in response to a mode selection signal.

Abstract: A reconfigurable power detector is described. The reconfigurable power detector includes a first power detector circuit. The first power detector circuit includes a pair of coupled first-type transistors to switch a first-type positive output and a first-type negative output. The reconfigurable power detector includes a second power detector circuit. The second power detector circuit includes a pair of coupled second-type transistors to switch a second-type positive output and a second-type negative output. The reconfigurable power detector includes a switch matrix. The switch matrix includes switches to select the second-type positive output and the second-type negative output in a first configuration, the first-type positive output and the first-type negative output in a second configuration, and the first-type positive output and the second-type positive output in a third configuration.

Abstract: A programmable filter includes a first programmable filter instance comprising a first adjustable active inductance capacitively coupled to a signal receive path, the capacitive coupling comprising at least one adjustable capacitance, the adjustable active inductance and the at least one adjustable capacitance configurable to provide a filter response at a first selected frequency, and a second programmable filter instance comprising a second adjustable active inductance capacitively coupled to the signal receive path, the capacitive coupling comprising at least one adjustable capacitance, the second adjustable active inductance and the at least one adjustable capacitance configurable to provide a filter response at a second selected frequency.

Abstract: An apparatus is disclosed for phase-shifting signals. In example implementations, the apparatus includes a phase shifter. The phase shifter includes a first port, a second port, a vector modulator coupled to the first port, and a signal phase generator. The signal phase generator includes multiple amplifiers coupled between the vector modulator and the second port. The signal phase generator also includes multiple capacitors that couple the multiple amplifiers together to form a loop. Each respective capacitor of the multiple capacitors is coupled between a respective pair of consecutive amplifiers of the multiple amplifiers to form the loop.

Abstract: A reconfigurable power detector is described. The reconfigurable power detector includes a first power detector circuit. The first power detector circuit includes a pair of coupled first-type transistors to switch a first-type positive output and a first-type negative output. The reconfigurable power detector includes a second power detector circuit. The second power detector circuit includes a pair of coupled second-type transistors to switch a second-type positive output and a second-type negative output. The reconfigurable power detector includes a switch matrix. The switch matrix includes switches to select the second-type positive output and the second-type negative output in a first configuration, the first-type positive output and the first-type negative output in a second configuration, and the first-type positive output and the second-type positive output in a third configuration.

Abstract: During an uplink TDD slot, an UL UE transmits an UL signal that occupies a slot frequency range. Similarly, during a DL TDD slot, a DL UE receives a DL signal that occupies the slot frequency range. But during an SBFD slot, a UL UE transmits a UL signal that occupies only a first sub-band of the slot frequency range. Similarly, a DL UE receives a DL signal during an SBFD slot that occupies only a second sub-band of the slot frequency range. The second sub-band is distinct from the first sub-band. The DL UE may thus mitigate UE-to-UE interference during an SBFD slot by filtering the DL signal to substantially block the second sub-band from being received at the DL UE.

Abstract: An apparatus is disclosed for bidirectional variable gain amplification. In an example aspect, an apparatus comprises an antenna element of an antenna array and a wireless transceiver. The wireless transceiver comprises a transmit path coupled to the antenna element, a receive path coupled to the antenna element, and a phase shifter disposed in both the transmit path and the receive path. The phase shifter is configured to operate in an active mode and comprises a first bidirectional variable gain amplifier and a second bidirectional variable gain amplifier.

Abstract: In certain aspects, a receiver includes first amplifiers, wherein each one of the first amplifiers comprises an input and an output. The receiver also includes second amplifiers, wherein each one of the second amplifiers comprises an input and an output, and the outputs of the second amplifiers are coupled to a combining node. The receiver also includes transmission lines, wherein each one of the transmission lines is coupled between the output of a respective one of the first amplifiers and the input of a respective one of the second amplifiers. The receiver further includes a load coupled to the combining node, and receiver elements, wherein each one of the receiver elements comprises an input and an output, and the output of each one of the receiver elements is coupled to the input of a respective one of the first amplifiers.

Abstract: An apparatus is disclosed for bidirectional amplification with phase-shifting. In example implementations, an apparatus includes a phase shifter with a bidirectional amplifier. The bidirectional amplifier includes a first transistor coupled between a first plus node and a second minus node, a second transistor coupled between a first minus node and a second plus node, a third transistor coupled between the first plus node and the second minus node, and a fourth transistor coupled between the first minus node and the second plus node. The bidirectional amplifier also includes a fifth transistor coupled between the first plus node and the second plus node, a sixth transistor coupled between the first minus node and the second minus node, a seventh transistor coupled between the first plus node and the second plus node, and an eighth transistor coupled between the first minus node and the second minus node.

Abstract: The present disclosure provides an apparatus that includes a first mixer circuit configured to convert between an RF signal and an IF signal based at least in part on an local oscillator (LO) signal. The first mixer circuit is electrically coupled to a first node that is configured to receive the LO signal and a first bias voltage, a second node that is configured to receive the RF signal or the IF signal, and a third node that is configured to provide the IF signal or the RF signal. The apparatus further includes a second mixer circuit electrically coupled to a fourth node configured to receive the LO signal and a second bias voltage, the second node, and the third node. The second bias voltage has a voltage level that is offset from the first bias voltage.

Abstract: An RF driver circuit may include a wideband output impedance matching and gain circuit, a wideband input impedance matching and gain circuit, and a summer configured to sum the outputs of the wideband output impedance matching and gain circuit and wideband input impedance matching and gain circuit. The wideband output impedance matching and gain circuit and wideband input impedance matching and gain circuit may collectively provide the gain of the RF driver circuit. The wideband output impedance matching circuit may have a source follower configuration. The wideband input impedance matching circuit may have a common gate configuration. Controllable bias voltages may be used to maintain a constant gain and interface impedances in multiple modes of operation.

Abstract: An apparatus is disclosed for complementary variable gain amplification. In an example aspect, the apparatus includes a variable gain amplifier that includes multiple amplifiers. The multiple amplifiers include at least one first amplifier and at least one second amplifier cascaded together in series. The first amplifier includes a first set of transistors having a first doping type. At least a portion of the first set of transistors is configured to implement a first current mirror. The second amplifier includes a second set of transistors having a second doping type. At least a portion of the second set of transistors is configured to implement a second current mirror. The second current mirror is coupled to the first current mirror.

Abstract: A receiver may include a time-interleaved charge sampler comprising a charge sampler switch in series with a charge sampler capacitor. The receiver may also include a current buffer configured to drive the time-interleaved charge sampler.

Abstract: An apparatus is disclosed for current-mode filtering using current steering. In an example aspect, the apparatus includes a filter. The filter includes a current-steering node, a first output node, a second output node, a wideband path, and a narrowband path. The wideband path is coupled between the current-steering node and the first output node. The wideband path includes a wideband low-pass filter configured to pass frequencies within a wide passband. The narrowband path is coupled between the current-steering node and the second output node. The narrowband path includes a narrowband low-pass filter configured to pass a portion of the frequencies that are within a narrow passband.

Abstract: A method and system for self-powering a clock input buffer is disclosed. The system includes an input node adapted to receive an alternating current (AC) signal having an instantaneous voltage oscillating between a minimum voltage and a maximum voltage. The system includes a pass transistor having a voltage controlled terminal, a first transfer terminal, and a second transfer terminal. The first transfer terminal connects to the input node and the second transfer terminal connects to a power node. The circuit also includes a plurality of transistors adapted to form a logic gate connected to the power node, and having a sensing terminal connected to the input node and an output terminal connected to the voltage controlled terminal. The logic gate produces a control voltage on the output terminal in response to an input voltage on the sensing terminal. The circuit also includes an energy-storage element having a first terminal connected to the power node.

Abstract: A bias circuit includes a differential amplifier including at least two field effect transistors each having a gate, a source and a drain, a gain of the differential amplifier being based at least in part on a gate bias voltage, and a temperature compensation element selectively coupled to the gate of each of the two field effect transistors, the temperature compensation element configured to provide a compensated gate bias voltage across a temperature range.

Abstract: An apparatus is disclosed for complementary variable gain amplification. In an example aspect, the apparatus includes a variable gain amplifier that includes multiple amplifiers. The multiple amplifiers include at least one first amplifier and at least one second amplifier cascaded together in series. The first amplifier includes a first set of transistors having a first doping type. At least a portion of the first set of transistors is configured to implement a first current mirror. The second amplifier includes a second set of transistors having a second doping type. At least a portion of the second set of transistors is configured to implement a second current mirror. The second current mirror is coupled to the first current mirror.

Abstract: An apparatus comprising a transmit path, a plurality of local oscillators and a control unit. The control unit may be configured to: receive an upcoming resource block (RB) allocation; determine whether the upcoming RB allocation is the same as the current RB allocation; in response to determining that the upcoming RB allocation is different than the current RB allocation: select an unused LO of the plurality of LOs; determine whether a number of allocated RBs associated with the upcoming RB allocation is greater than a threshold; and in response to determining that the number of allocated RBs associated with the upcoming RB allocation is not greater than the threshold, tune the selected LO to a frequency corresponding to the upcoming RB allocation.