Abstract: A memory cell including a substrate having a first doped region and a second doped region spaced apart from each other and defining a channel region therebetween, a floating gate including a first end over the channel region and a second end over the first doped region, a control gate including a first portion arranged laterally adjacent to the second end of the floating gate and a second portion arranged over and overlapping the second end of the floating gate, a word line overlapping the channel region, the first end of the floating gate, and the second portion the control gate, a first insulation member separating the floating gate, the control gate and the word line from the substrate; a second insulation member separating the floating gate from the control gate, and a third insulation member separating the floating gate and the control gate from the word line.

Abstract: A semiconductor interconnect structure including a conductive layer, a plurality of interconnect vias and a pad is presented. The interconnect vias are formed over the conductive layer and the pad having a substantially flat surface is formed over the plurality of interconnect vias. The conductive layer may be a conductive line and/or a conductive plate connected to a conductive line.

Abstract: A method of forming a uniform WL over the MCEL region and resulting device are provided. Embodiments include providing a substrate having a MCEL region, a HV region and a logic region, separated by an isolation region; forming a plurality of CG stacks over the MCEL region, and a plurality of CG dummy stacks over the HV region and the logic region, respectively; forming first and second overlying polysilicon layers with a spacer therebetween, an EG and a WL on the MCEL region formed; planarizing the second polysilicon layer down to upper surface of the plurality of CG stacks and the plurality of CG dummy stacks; and removing portions of the second polysilicon layer in-between the plurality of CG stacks and around the plurality of CG dummy stacks.

Abstract: Methods of producing integrated circuits are provided. An exemplary method includes patterning a source line photoresist mask to overlie a source line area of a substrate while exposing a drain line area. The source line area is between a first and second memory cell and the drain line area is between the second and a third memory cell. A source line is formed in the source line area. A source line dielectric is concurrently formed overlying the source line while a drain line dielectric is formed overlying a drain line area. A drain line photoresist mask is patterned to overlie the source line in an active section while exposing the source line in a strap section, and while exposing the drain line area. The drain line dielectric is removed from over the drain line area while a thickness of the source line dielectric in the strap section is reduced.

Abstract: Methods of producing integrated circuits are provided. An exemplary method includes patterning a source line photoresist mask to overlie a source line area of a substrate while exposing a drain line area. The source line area is between a first and second memory cell and the drain line area is between the second and a third memory cell. A source line is formed in the source line area. A source line dielectric is concurrently formed overlying the source line while a drain line dielectric is formed overlying a drain line area. A drain line photoresist mask is patterned to overlie the source line in an active section while exposing the source line in a strap section, and while exposing the drain line area. The drain line dielectric is removed from over the drain line area while a thickness of the source line dielectric in the strap section is reduced.

Abstract: Integrated circuits and methods of producing the same are provide. In an exemplary embodiment, a method includes determining a memory area of the integrated circuit, and forming a select layer overlying the substrate. A portion of the select layer is selectively etched to form a select gate within the memory area. A concentration of an indicator is measured in an etch off-gas during the selective etching of the select layer, and the selective etching of the select layer is terminated when the concentration of the indicator crosses an end point determination concentration.

Abstract: A capacitor and method of forming a capacitor are presented. The capacitor includes a substrate having a capacitor region in which the capacitor is disposed. The capacitor includes first, second and third sub-capacitors (C1, C2 and C3). The C1 comprises a metal oxide semiconductor (MOS) capacitor which includes a gate on the substrate. The gate includes a gate electrode over a gate dielectric. A first C1 plate is served by the gate electrode, a second C1 plate is served by the substrate of the capacitor region and a C1 capacitor dielectric is served by the gate dielectric. The C2 includes a back-end-of-line (BEOL) vertical capacitor disposed in ILD layers with metal levels and via levels. A plurality of metal lines are disposed in the metal levels.

Abstract: Integrated circuits with dummy contacts and methods for fabricating such integrated circuits are provided. The method includes forming an interlayer dielectric overlying an electronic component and a substrate, wherein the interlayer dielectric has an interlayer dielectric top surface. An active contact is formed through the interlayer dielectric and forms an electrical connection with the electronic component. A dummy contact is formed within the interlayer dielectric where the dummy contact extends to a dummy contact termination point between the interlayer dielectric top surface and the substrate such that an insulator is positioned between the dummy contact termination point and the electronic component.

Abstract: A capacitor and method of forming a capacitor are presented. The capacitor includes a substrate having a capacitor region in which the capacitor is disposed. The capacitor includes first, second and third sub-capacitors (C1, C2 and C3). The C1 comprises a metal oxide semiconductor (MOS) capacitor which includes a gate on the substrate. The gate includes a gate electrode over a gate dielectric. A first C1 plate is served by the gate electrode, a second C1 plate is served by the substrate of the capacitor region and a C1 capacitor dielectric is served by the gate dielectric. The C2 includes a back-end-of-line (BEOL) vertical capacitor disposed in ILD layers with metal levels and via levels. A plurality of metal lines are disposed in the metal levels. The metal lines of a metal level are grouped in alternating first and second groups, the first group serves as first C2 plates and second group serves as second.