Abstract: A “weak” undriven state is defined as a signal state, distinguished from conventional unknown and high impedance states, and methods of representing this “weak” undriven state in circuit modelling and power aware digital/mixed-signal simulations for comprehensive and complete RTL-level design verification. The conventional unknown state refers to a circuit element that is powered but has an unknown value, a circuit element that is not powered, or a circuit element having an undriven, floating signal. The unknown state is modified, and the “weak” undriven state refers to a circuit element that is not powered and has an unknown value. The “weak” undriven state can have an electrically high impedance to known supply or ground when no other circuit element is active. The “weak” undriven state distinction is particularly useful to model and verify circuit designs known to be resilient to “weak” undriven states, using event driven logic circuit simulators.

Abstract: Presented herein are system(s) and method(s) for motion estimation using camera movements. In one embodiment, there is presented a video camera system for providing video data. The video camera system comprises a video camera, and a circuit. The video camera captures video data. The circuit records information that indicates tracking movements of the video camera.

Abstract: Presented herein are a system, method, and apparatus for retrieving an object from memory. The object can be stored in a manner, such that the first byte of the object and the last byte of the object are in the middle of the memory data words. The object is retrieved by a direct memory access controller. The direct memory access controller, when provided with a read transaction with the starting address and the ending address of the object, retrieves the data words storing the object, and overwrites the portions of the data word that precede and follow the object.

Abstract: The present invention is directed to a line address computer for calculating the starting line addresses for lines of a decoded frame. The starting addresses for a display frame are provided to the line address computer by a host processor. The line address computer determines the starting line addresses for subsequent lines by appropriately incrementing the line addresses of previous lines.

Abstract: Presented herein are video decoding system(s), method(s), and apparatus for repeating a last line to a scalar or compositor or capture. A first parameter is provided to a first register indicating that a picture comprises a first number of lines, and a second parameter is provided to a second register, indicating that the picture comprises a second number of lines.

Abstract: Presented herein are systems and methods for clock rate determination. A bitstream is sampled by sampling a transmitted clock signal at a rate corresponding to a receiver clock signal, and measuring an average number of consecutive samples that have a same state selected from a first state and a second state.

Abstract: Presented herein is a system for storing macroblocks for concatenated frames. A decoder system comprises a frame buffer. The frame buffer comprises one or more rows. A particular one of the rows stores macroblocks from a plurality of frames.

Abstract: A method and system for testing a memory controller are provided herein. A test sequence may be generated within the memory controller. A test output may also be generated within the memory controller, where the test output is associated with the test sequence. The test output may then be verified. The test sequence may comprise one or more of a control command, a memory address, and/or a DQM signal. The test output may be generated by a sequencer. The test output may be verified by a cyclic redundancy check (CRC) module. The test sequence may also comprise random write data. The random write data may be communicated to a memory controller write data output via a write data bus.

Abstract: Presented herein are systems and methods for pixel reordering and selection. A decoded frame is stored in a frame buffer with a particular pixel order and byte order. A pixel feeder fetches portions of the decoded frame and stores portions of the frame in a double buffer with the same pixel order and byte order. An endian swizzle converts the byte ordering to a predetermined format, as needed. Reordering logic changes the pixel order to a predetermined order. Selection logic selects luma and chroma pixels from fetched pixels and provides the luma pixels to a luma pixel register, chroma Cr pixels to a chroma Cr pixel register, and chroma Cb pixels to a chroma Cb pixel register.

Abstract: Presented herein is a system and method for a line address computer for providing line addresses in multiple contexts for interlaced to progressive conversion. A feeder fetches a first line from a top field, fetches a first line from a bottom field corresponding to the top field, after fetching the first line from the top field, and fetches a second line from the top field after fetching the first line from the bottom field. The second line from the top field is adjacent to the first line in the top field.

Abstract: Presented herein is a line address computer for providing chroma coefficients to a chroma filter. At each horizontal synchronization pulse, the line address computer provides a set of interpolation weights to a chroma filter. The chroma filter uses the provided set of weights to interpolate pixels in chroma pixel positions in a display format from chroma pixels in another format.

Abstract: Methods of setting numerically controlled delay lines using step sizes based on a delay locked loop lock value are presented herein. In one embodiment, a method may comprise, for example, one or more of the following: calculating an offset value for at least one NCDL; and interpolating a new offset value for the at least one NCDL, based on a change in a delay locked loop (DLL) output value from a previous DLL output value to a new DLL output value.

Abstract: Presented herein is a system and method for improving video data compression by varying quantization bits based on a region within picture. In one embodiment, there is presented a method for encoding video data. The method comprises dividing a picture into a plurality of blocks; compressing a particular one of the plurality of blocks with lossless compression; measuring how far the particular block is from a center of the picture; and compressing the particular one of the blocks with lossy compression, wherein information loss is based on how far the particular block is from the center of the picture.

Abstract: Presented herein are system(s) and method(s) for motion estimation using camera movements. In one embodiment, there is presented a video camera system for providing video data. The video camera system comprises a video camera, and a circuit. The video camera captures video data. The circuit records information that indicates tracking movements of the video camera.

Abstract: A method and system for testing a memory controller are provided herein. A test sequence may be generated within the memory controller. A test output may also be generated within the memory controller, where the test output is associated with the test sequence. The test output may then be verified. The test sequence may comprise one or more of a control command, a memory address, and/or a DQM signal. The test output may be generated by a sequencer. The test output may be verified by a cyclic redundancy check (CRC) module. The test sequence may also comprise random write data. The random write data may be communicated to a memory controller write data output via a write data bus.

Abstract: Presented herein are systems and methods for clock rate determination. A bitstream is sampled by sampling a transmitted clock signal at a rate corresponding to a receiver clock signal, and measuring an average number of consecutive samples that have a same state selected from a first state and a second state.

Abstract: Presented herein are video decoding system(s), method(s), and apparatus for repeating a last line to a scalar or compositor or capture. A first parameter is provided to a first register indicating that a picture comprises a first number of lines, and a second parameter is provided to a second register, indicating that the picture comprises a second number of lines.

Abstract: Presented herein are systems and methods for repeating a last picture. A first frame is provided for display a first time. After displaying the first frame, the information about a second frame to display is awaited. The first frame is repeated if the information regarding the second frame is not received before a predetermined time.

Abstract: Presented herein is a system and method for a line address computer for providing line addresses in multiple contexts for interlaced to progressive conversion. A feeder fetches a first line from a top field, fetches a first line from a bottom field corresponding to the top field, after fetching the first line from the top field, and fetches a second line from the top field after fetching the first line from the bottom field. The second line from the top field is adjacent to the first line in the top field.

Abstract: Presented herein are systems and methods for pixel reordering and selection. A decoded picture is stored in a frame buffer with a particular pixel order and byte order. A input data write unit fetches portions of the decoded picture and stores portions of the picture in a double buffer with the same pixel order and byte order. An endian swizzle converts the byte ordering to a predetermined format, as needed. Reordering logic changes the pixel order to a predetermined order. Selection logic selects luma and chroma pixels from fetched pixels and provides the luma pixels to a luma pixel register, chroma Cr pixels to a chroma Cr pixel register, and chroma Cb pixels to a chroma Cb pixel register.